IC-工具篇--VCS使用教程-卷二（202004013）

引言

本文在上一讲逐渐熟悉了VCS的开关选项后，下面继续介绍VCS的使用，我始终关注于熟悉工具的使用，在本系列中，对Verilog的语法不作深入研究，这样可以加快前进的步伐。也为了加快从FPGA中转变到IC领域来。在本文中将介绍VCS 调试基础。

1、基础理论讲义

—Afer completing this unit ,you should be able to:

1. Describe three methods of debugging Verilog code using VCS
2. Invoke UCLI debugger
3. Debug Verilog designs using UCLI

–VCS Debugging Suport
4. Trance and locate causes of errors
5. Three general debugging methods:

6. Verilog SystemVerilog System Task calls
   VCS UCLI
   VCS DVE(GUI)

7. Four factors to consider:
   simulation speed
   signal visibility
   sgnal tractability
   usability

Verilog System Task For Debugging 利用verilog的系统函数

1. Debug visibility:

• $ display prints formatted message to console
• $ strobe Like$dispaly except printing is delayed until all events in the current time step have executed
• $ monitor Monitor signals listed and prints formatted message whenever one of the listed signals changes
• $ time returns current simulation time as a 64bits integer

2. Stopping simulations:
   $stop halts simulation lie a breakpoint
   $finish halts simulation and terminated the simulation session

3. Simulation stimulus and reference:

• $rea$