ONFI 5.1协议

4. Data Interface and Timing

SDR: VccQ 1.8V or 3.3V

NV-DDR: VccQ 1.8V or 3.3V

NV-DDR2: VccQ 1.8V，支持on die termination and differential signaling，比DDR速度更快

NV-DDR3: VccQ 1.2V

NV-LPDDR4: VccQ 1.2V，LTT

4.1 SDR

4.2 NV-DDR

4.3 NV-DDR2/NV-DDR3

4.4 NV-LPDDR4

5. 信号质量相关

5.1 ODT

        On-die termination is an optional capability that may be employed to meet higher speeds in particular topologies. On-die termination can improve signal quality by reducing signal reflection through internal termination resistance adjustment.

    self-termination, matrix termination(enables a combination of Target and non-Target termination to be specified)

        可调节的电阻值，类似滑动变阻器

        On-die termination on the DQ[7:0], DQS_t, DQS_c, RE_t, and RE_c signals.

        On-die termination is supported for the NV-DDR2, NV-DDR3 and NV-LPDDR4.

5.1.1 Self-termination ODT

5.1.2 Matrix Termination

5.2 ZQ calibration

        optional for the NV-DDR2, recommended for the NV-DDR3 interface over 400MT/s speed, required for the NV-LPDDR4.

        calibrate NAND Ron values and may also be used to calibrate ODT values.

        the calibrated values are transferred from the calibration engine to NAND IO, which updates the output driver and on-die termination values.

        Polling status to check calibration success or not.

分类：Host side ZQ calibration        NAND side ZQ calibration

校准的方法：使用外部参考电阻

5.3 DCC training

        DCC(Duty Cycle Correction) Training is the feature for the NAND to compensate duty cycle mismatch of RE_t/c signal. The internal RE clock is being calibrate during data output.

主要目的：系统性校正系统时钟、数据时钟所有时钟信号的占空比偏差，确保高速数据传输的时序准确性

        DCC Training shall be performed after the ZQ calibration is completed.

1. set DCCE_EN
2. Random Data Out command a page size with the address 00h
3. Polling status

5.4 read training

        Read/Write DQ Training is the feature for the host to align DQS and DQ signals caused by unmatched DQS path.

5.5 write training

        Read/Write DQ Training is the feature for the host to align DQS and DQ signals caused by unmatched DQS path.

5.5. 1 Write Duty Cycle Adjustment(WDCA)

        Write Duty Cycle Adjustment (WDCA) is an optional feature that provides a way to compensate for input DQS duty cycle loss at the NAND device.

        调节WE#, ALE, CLE 等写入控制信号的占空比 (Duty Cycle)，即时钟信号在一个周期内高电平持续时间与整个周期时间的比值

5.5.2 Write DQ Training (Rx Side)

5.5.3 Write DQ Training (Tx Side)

        After writing data to the NAND with 63h command, the data can be read back with 64h command followed by LUN address and the results shall be compared with“expected” data to see if further training (DQ delay) is needed.

5.6 DLL

        调整DQS与DQ的相位，理论上DQS与DQ需要对齐

6. IO strength

7. 时序相关

7.1 General Parameters

7.2 SDR

7.3 NV-DDR

7.4 NV-DDR2/NV-DDR3

7.5 NV-LPDDR4

7.6 SDR timing diagrams

7.6.1 Command Latch Timings

7.6.2 Address Latch Timings

7.6.3 Data Input Cycle Timings

7.6.4 Data Output Cycle Timings

7.6.5 Data Output Cycle Timings (EDO)

7.7 NV-DDR timing diagrams

7.7.1 Command Cycle Timings

7.7.2 Address Cycle Timings

7.7.3 Data Input Cycle Timings

7.7.4 Data Output Cycle Timings

7.8 NV-DDR2/NV-DDR3/NV-LPDDR4 timing diagrams

7.8.1 Command Cycle Timings

7.8.2 Address Cycle Timings

7.8.3 Data Input Cycle Timings

7.8.4 Data Output Cycle Timings

8. Command Definition

9. Feature Parameter Definitions