LCD160液晶显示驱动设计（Hello word *^_^*,I am baifengqiang）

本文介绍了使用FPGA来驱动LCD1602液晶显示模块的方法，包括20ms延时设置、寄存器配置、显示模式选择等步骤，并展示了详细的Verilog代码实现，最终实现显示"I am baifengqiang"和"Hello World*^_^*"的文本。

关于LCD1602液晶的驱动显示，通过C语言来写，还是挺简单（吹个牛，主要是多年不写，忘得差不多了），就是寄存器初始状态的配置等等，在这里用FPGA来驱动，需要注意几点：

1.板卡上电之后之后，有一个15ms的延时，在此我们设置20ms，利用计数器可以完成。

2.寄存器的配置，首先确定是8bit模式还是4bit模式，在此，我们选择第一种，另外还需配置屏幕是1行显示或者2行显示，在此我们选择第二种，综上所述，按照LCD1602的datasheet可知配置成8'h38。

3.关闭LCD1602，必须先关闭，后面才能驱动，那么配置成8'h08。

4.重置DDRAM中的数据，配置寄存器位8'h01。

5.设置显示模式，配置为8'h06。

6.前面设置了关闭模式，这里打开显示模式，配置为8'h0c。

7.给第一行显示数据的初始地址，80h。

8.输入第一行显示的字符。

9.输入第二行显示字符的首地址，c0h。

10.输入第二行显示字符。

具体代码如下:

/*************************************************
* Module Name : lcd1602_driver
* Engineer : Bai fengqiang
* Target Device : EP2C8Q208C8
* Tool versions : Quartus II 13.1
* Create Date : 2017-7-12
* Revision : v1.0
* Description :
**************************************************/
module lcd_1602_design
(
input clk,
input rst_n,

output lcd_en, // lcd enable
output reg lcd_rs, // record,statement
output lcd_rw,
output reg [7:0] lcd_data,
output reg [9:0] delay_20ms_cnt,
output delay_done,
output lcd_write_flag,
output reg [6:0] delay_cnt2

);

parameter [127:0] line_rom1 = "I am baifengqiang";
parameter [127:0] line_rom2 = "Hello World*^_^*";

//--------------------------------------延时20ms计数，因为上电之后系统需要稳定至少15ms

parameter delay_20ms=10'd1000;

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
delay_20ms_cnt <= 0;
else
begin
if(delay_20ms_cnt<delay_20ms)
delay_20ms_cnt<=delay_20ms_cnt+1;
else
delay_20ms_cnt<=delay_20ms_cnt;
end

end

assign delay_done=(delay_20ms_cnt==delay_20ms)?1'b1:1'b0;

parameter delay_cnt_en=7'd100;

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
delay_cnt2 <= 0;
else
if(delay_done)
begin
if(delay_cnt2<delay_cnt_en)
delay_cnt2<=delay_cnt2+1;
else
delay_cnt2<=0;
end
else
delay_cnt2<=0;

end

assign lcd_en=(delay_cnt2>=delay_cnt_en/2)?1'b0:1'b1;
assign lcd_write_flag=(delay_cnt2==delay_cnt_en-1'b1)?1'b1:1'b0;
assign lcd_rw=1'b0;

// Gray code : 40 states
parameter IDLE = 8'h00; // IDLE
// lcd init
parameter DISP_SET = 8'h01; // display mode
parameter DISP_OFF = 8'h03; // off display
parameter CLR_SCR = 8'h02; // clear the lcd
parameter CURSOR_SET1 = 8'h06; // cursor set
parameter CURSOR_SET2 = 8'h07; // on display, cursor set
// display 1th line
parameter ROW1_ADDR = 8'h05;
parameter ROW1_0 = 8'h04;
parameter ROW1_1 = 8'h0C;
parameter ROW1_2 = 8'h0D;
parameter ROW1_3 = 8'h0F;
parameter ROW1_4 = 8'h0E;
parameter ROW1_5 = 8'h0A;
parameter ROW1_6 = 8'h0B;
parameter ROW1_7 = 8'h09;
parameter ROW1_8 = 8'h08;
parameter ROW1_9 = 8'h18;
parameter ROW1_A = 8'h19;
parameter ROW1_B = 8'h1B;
parameter ROW1_C = 8'h1A;
parameter ROW1_D = 8'h1E;
parameter ROW1_E = 8'h1F;
parameter ROW1_F = 8'h1D;
// display 2th line
parameter ROW2_ADDR = 8'h1C;
parameter ROW2_0 = 8'h14;
parameter ROW2_1 = 8'h15;
parameter ROW2_2 = 8'h17;
parameter ROW2_3 = 8'h16;
parameter ROW2_4 = 8'h12;
parameter ROW2_5 = 8'h13;
parameter ROW2_6 = 8'h11;
parameter ROW2_7 = 8'h10;
parameter ROW2_8 = 8'h30;
parameter ROW2_9 = 8'h31;
parameter ROW2_A = 8'h33;
parameter ROW2_B = 8'h32;
parameter ROW2_C = 8'h36;
parameter ROW2_D = 8'h37;
parameter ROW2_E = 8'h35;
parameter ROW2_F = 8'h34;

//---------------------------------------
reg [5:0] current_state, next_state;
// FSM: always1
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
current_state <= IDLE;
else if(lcd_write_flag)
current_state <= next_state;
end

//---------------------------------------
// FSM: always2
always@*
begin
case(current_state)
// lcd init
IDLE : next_state = DISP_SET;
DISP_SET : next_state = DISP_OFF;
DISP_OFF : next_state = CLR_SCR;
CLR_SCR : next_state = CURSOR_SET1;
CURSOR_SET1 : next_state = CURSOR_SET2;
CURSOR_SET2 : next_state = ROW1_ADDR;
// display 1th line
ROW1_ADDR : next_state = ROW1_0;
ROW1_0 : next_state = ROW1_1;
ROW1_1 : next_state = ROW1_2;
ROW1_2 : next_state = ROW1_3;
ROW1_3 : next_state = ROW1_4;
ROW1_4 : next_state = ROW1_5;
ROW1_5 : next_state = ROW1_6;
ROW1_6 : next_state = ROW1_7;
ROW1_7 : next_state = ROW1_8;
ROW1_8 : next_state = ROW1_9;
ROW1_9 : next_state = ROW1_A;
ROW1_A : next_state = ROW1_B;
ROW1_B : next_state = ROW1_C;
ROW1_C : next_state = ROW1_D;
ROW1_D : next_state = ROW1_E;
ROW1_E : next_state = ROW1_F;
ROW1_F : next_state = ROW2_ADDR;
// display 2th line
ROW2_ADDR : next_state = ROW2_0;
ROW2_0 : next_state = ROW2_1;
ROW2_1 : next_state = ROW2_2;
ROW2_2 : next_state = ROW2_3;
ROW2_3 : next_state = ROW2_4;
ROW2_4 : next_state = ROW2_5;
ROW2_5 : next_state = ROW2_6;
ROW2_6 : next_state = ROW2_7;
ROW2_7 : next_state = ROW2_8;
ROW2_8 : next_state = ROW2_9;
ROW2_9 : next_state = ROW2_A;
ROW2_A : next_state = ROW2_B;
ROW2_B : next_state = ROW2_C;
ROW2_C : next_state = ROW2_D;
ROW2_D : next_state = ROW2_E;
ROW2_E : next_state = ROW2_F;
ROW2_F : next_state = ROW1_ADDR;
default : next_state = IDLE ;
endcase
end

//---------------------------------------
// FSM: always3
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
lcd_rs <= 0;
lcd_data <= 8'hXX;
end
else if(lcd_write_flag)
begin
// write statement
case(next_state)
IDLE : lcd_rs <= 0; //statement
//lcd init
DISP_SET : lcd_rs <= 0; //statement
DISP_OFF : lcd_rs <= 0; //statement
CLR_SCR : lcd_rs <= 0; //statement
CURSOR_SET1 : lcd_rs <= 0; //statement
CURSOR_SET2 : lcd_rs <= 0; //statement
// display 1th line
ROW1_ADDR : lcd_rs <= 0; //statement
ROW1_0 : lcd_rs <= 1; //record
ROW1_1 : lcd_rs <= 1; //record
ROW1_2 : lcd_rs <= 1; //record
ROW1_3 : lcd_rs <= 1; //record
ROW1_4 : lcd_rs <= 1; //record
ROW1_5 : lcd_rs <= 1; //record
ROW1_6 : lcd_rs <= 1; //record
ROW1_7 : lcd_rs <= 1; //record
ROW1_8 : lcd_rs <= 1; //record
ROW1_9 : lcd_rs <= 1; //record
ROW1_A : lcd_rs <= 1; //record
ROW1_B : lcd_rs <= 1; //record
ROW1_C : lcd_rs <= 1; //record
ROW1_D : lcd_rs <= 1; //record
ROW1_E : lcd_rs <= 1; //record
ROW1_F : lcd_rs <= 1; //record
// display 2th line
ROW2_ADDR : lcd_rs <= 0; //statement
ROW2_0 : lcd_rs <= 1; //record
ROW2_1 : lcd_rs <= 1; //record
ROW2_2 : lcd_rs <= 1; //record
ROW2_3 : lcd_rs <= 1; //record
ROW2_4 : lcd_rs <= 1; //record
ROW2_5 : lcd_rs <= 1; //record
ROW2_6 : lcd_rs <= 1; //record
ROW2_7 : lcd_rs <= 1; //record
ROW2_8 : lcd_rs <= 1; //record
ROW2_9 : lcd_rs <= 1; //record
ROW2_A : lcd_rs <= 1; //record
ROW2_B : lcd_rs <= 1; //record
ROW2_C : lcd_rs <= 1; //record
ROW2_D : lcd_rs <= 1; //record
ROW2_E : lcd_rs <= 1; //record
ROW2_F : lcd_rs <= 1; //record
endcase

// write lcd_data
case(next_state)
IDLE : lcd_data <= 8'hxx;
//lcd init
DISP_SET : lcd_data <= 8'h38; //set 16X2,5X7 ,8 bits record
DISP_OFF : lcd_data <= 8'h08; //off display
CLR_SCR : lcd_data <= 8'h01; //clear lcd
CURSOR_SET1 : lcd_data <= 8'h06; //cursor set
CURSOR_SET2 : lcd_data <= 8'h0C; //on display
// display 1th line
ROW1_ADDR : lcd_data <= 8'h80;
ROW1_0 : lcd_data <= line_rom1[127:120];
ROW1_1 : lcd_data <= line_rom1[119:112];
ROW1_2 : lcd_data <= line_rom1[111:104];
ROW1_3 : lcd_data <= line_rom1[103: 96];
ROW1_4 : lcd_data <= line_rom1[ 95: 88];
ROW1_5 : lcd_data <= line_rom1[ 87: 80];
ROW1_6 : lcd_data <= line_rom1[ 79: 72];
ROW1_7 : lcd_data <= line_rom1[ 71: 64];
ROW1_8 : lcd_data <= line_rom1[ 63: 56];
ROW1_9 : lcd_data <= line_rom1[ 55: 48];
ROW1_A : lcd_data <= line_rom1[ 47: 40];
ROW1_B : lcd_data <= line_rom1[ 39: 32];
ROW1_C : lcd_data <= line_rom1[ 31: 24];
ROW1_D : lcd_data <= line_rom1[ 23: 16];
ROW1_E : lcd_data <= line_rom1[ 15: 8];
ROW1_F : lcd_data <= line_rom1[ 7: 0];
// display 2th line
ROW2_ADDR : lcd_data <= 8'hC0;
ROW2_0 : lcd_data <= line_rom2[127:120];
ROW2_1 : lcd_data <= line_rom2[119:112];
ROW2_2 : lcd_data <= line_rom2[111:104];
ROW2_3 : lcd_data <= line_rom2[103: 96];
ROW2_4 : lcd_data <= line_rom2[ 95: 88];
ROW2_5 : lcd_data <= line_rom2[ 87: 80];
ROW2_6 : lcd_data <= line_rom2[ 79: 72];
ROW2_7 : lcd_data <= line_rom2[ 71: 64];
ROW2_8 : lcd_data <= line_rom2[ 63: 56];
ROW2_9 : lcd_data <= line_rom2[ 55: 48];
ROW2_A : lcd_data <= line_rom2[ 47: 40];
ROW2_B : lcd_data <= line_rom2[ 39: 32];
ROW2_C : lcd_data <= line_rom2[ 31: 24];
ROW2_D : lcd_data <= line_rom2[ 23: 16];
ROW2_E : lcd_data <= line_rom2[ 15: 8];
ROW2_F : lcd_data <= line_rom2[ 7: 0];
endcase
end
end

endmodule

仿真结果：