简单逻辑电路设计实验-CSDN博客

一、实验名称

简单逻辑电路设计

二、实验目的

（1）掌握门级建模语句

（2）掌握数据流级建模语法

（3)熟悉实例化语句

（4）理解端口连接规则

三、实验步骤

在Modelsim中创建工程，向工程添加文件，编译设计文件，运行仿真，调试结果

三、实验代码

module  tbs1;
reg  S1,S2n,S3n;
reg  [2:0]  A;
wire  [7:0]  Yn1,Yn2,Yn3;

initial
begin
    A=3'b000;{S1,S2n,S3n}=3'b101;
    #5  {S1,S2n,S3n}=3'b011;
    #5  {S1,S2n,S3n}=3'b100;
          #5  A = 3'b001;
          #5 A =3'b010;
          #5  A =3'b011;
          #5  A= 3'b100;
         #5 A =3'b101;
          #5 A =3'b110;
         #5  A= 3'b111;
          #5  $stop;
end

decoder3x8_1  mydecoder(Yn1,S1,S2n,S3n,A);
decoder3x8_2  mydecoder2(Yn1,S1,S2n,S3n,A);
decoder3x8_3  mydecoder3(.Yn(Yn3),.S1(S1),.S2n(S2n),.S3n(S3n),.A(A));
endmodule

module decoder3x8_1(Yn,S1,S2n,S3n,A);
input S1,S2n,S3n;
input [2:0] A;
output [7:0] Yn;

wire S2,S3;
wire A0n,A1n,A2n;

not(S2,S2n);
not(S3,S3n);
and(S,S1,S2,S3);

not (A0n,A[0]);
not (A1n,A[1]);
not (A2n,A[2]);

nand (Yn[0],A0n,A1n,A2n,S);
nand (Yn[1],A[0],A1n,A2n,S);
nand (Yn[2],A0n,A[1],A2n,S);
nand (Yn[3],A[0],A[1],A2n,S);
nand (Yn[4],A0n,A1n ,A[2],S);
nand (Yn[5],A[0],A1n,A[2],S);
nand (Yn[6],A0n,A[1],A[2],S);
nand (Yn[7],A[0],A[1],A[2],S);

endmodule

module decoder3x8_2 (Yn,S1,S2n,S3n,A);
input S1,S2n,S3n;
input [2:0] A;
output [7:0] Yn;

wire S2,S3;
wire A0n,A1n,A2n;
assign S2=~S2n;
assign S3=~S3n;
assign S=S1&S2&S3;
assign A0n=~A[0];
assign A1n=~A[1];
assign A2n=~A[2];
assign Yn[0]=~(A0n &A1n &A2n &S);
assign Yn[1]=~(A[0]& A1n & A2n &S);
assign Yn[2]=~(A0n & A[1]& A2n & S);
assign Yn[3]=~(A[0]& A[1]& A2n &S);
assign Yn[4]=~(A0n & A1n &A[2]&S);
assign Yn[5]=~(A[0]& A1n &A[2]&S);
assign Yn[6]=~(A0n & A[1]&A[2]&S);
assign Yn[7]=~(A[0]&A[1]& A[2]&S);

endmodule

module decoder3x8_3(Yn,S1,S2n,S3n,A);
input S1,S2n,S3n;
input [2:0] A;
output [7:0]Yn;
assign S=S1&(~S2n)&(~S3n);

assign Yn=(S==0)?8'b1111_1111:
(A==3'b000)?8'b1111_1110:
(A==3'b001)?8'b1111_1101:
(A==3'b010)?8'b1111_1011:
(A==3'b011)?8'b1111_0111:
(A==3'b100)?8'b1110_1111:
(A==3'b101)?8'b1101_1111:
(A==3'b110)?8'b1011_1111:
(A==3'b111)?8'b0111_1111:
8'b1111_1111;

endmodule