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ORCIDAmandeep Kaur 0005
Person information
- affiliation: Indian Institute of Technology Jodhpur (IIT Jodhpur), Department of Electrical Engineering, India
- affiliation (PhD 2019): Indian Institute of Technology Delhi (IIT Delhi), Department of electrical engineering, New Delhi, India
Other persons with the same name
- Amandeep Kaur — disambiguation page
- Amandeep Kaur 0001
![[0000-0003-4844-9299]](https://dblp.org/img/orcid-mark.12x12.png "0000-0003-4844-9299")
— Central University of Punjab, Bathinda, India - Amandeep Kaur 0002 — National Institute of Technology Hamirpur, Hamirpur, India
- Amandeep Kaur 0003 — Guru Nanak Dev University, Gurdaspur, India
- Amandeep Kaur 0004 — University of Cambridge, Cambridge, UK
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2020 – today
- 2026
[j10]Wilfred Kisku, Amandeep Kaur, Deepak Mishra:
Efficient Edge-AI with Binarized Neural Networks and CMOS Image Sensors: A Sparsity-Driven Approach. Circuits Syst. Signal Process. 45(1): 557-573 (2026)- [j9]Parminder Kaur, Amandeep Kaur:
A Fully Reconfigurable Low Offset Asymmetric Sense Amplifier Implementing Multiple Logic Gates for In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 73(6): 3813-3824 (2026) - [c23]Parminder Kaur, Charagundla Sai Laxman, Amandeep Kaur:
A Fully Reconfigurable and Adaptable Current-Source Based Sense Amplifier for Energy Efficient in-Memory Computing. VLSID 2026: 125-130 - [c22]Amandeep Kaur, Mukul Sarkar:
A Low Noise CMOS Image Sensor with Column-Parallel Readout. VLSID 2026: 275-280 - 2025
- [j8]Bibhudutta Satapathy, Sivaiah Naali, Amandeep Kaur:
A Multiply-by-Two Switched-Capacitor Amplifier with Reduced Sensitivity to Capacitive Mismatch. Circuits Syst. Signal Process. 44(3): 1545-1558 (2025) - [j7]Bibhudutta Satapathy, Karan Jadhav, Amandeep Kaur:
An Adaptive Body Tuned Sense Amplifier for Energy Efficient In-Memory Computing. IEEE Trans. Circuits Syst. II Express Briefs 72(5): 683-687 (2025) - [j6]Bibhudutta Satapathy, Utkarsh Srivastava, Amandeep Kaur:
An Asymmetric Dynamic Comparator for Low-Offset, Low-Noise, and High-Speed Applications. IEEE Trans. Instrum. Meas. 74: 1-8 (2025) - [c21]Wilfred Kisku, Azad Singh, Amandeep Kaur, Deepak Mishra:
ViT Coupled Efficient CMOS Image Sensor with Sparse Acquisition and Patch Selection. ISCAS 2025: 1-5 - [c20]Bibhudutta Satapathy, Dhananjay Harish Bhalwala, Amandeep Kaur:
An Asymmetric Static Comparator for RC Oscillator Achieving $21.6 \text{ppm} /{}^{\circ} \mathrm{C}$ Temperature-Stability. NewCAS 2025: 202-206 - [c19]Parminder Kaur, Amandeep Kaur:
LO-ASA: Low Offset Asymmetric Sense Amplifier for Digital In-Memory Computing in SRAM. NewCAS 2025: 331-335 - 2024
- [j5]Bibhudutta Satapathy, Amandeep Kaur:
A Dynamic Offset Reduction Technique to Mitigate the Effect of Threshold Mismatch in Energy Efficient Comparators. IEEE Access 12: 82111-82119 (2024) - [j4]Wilfred Kisku, Amandeep Kaur, Deepak Mishra:
An Intelligent System With Reduced Readout Power and Lightweight CNN for Vision Applications. IEEE Trans. Circuits Syst. Video Technol. 34(2): 1310-1315 (2024) - [c18]Wilfred Kisku, Amandeep Kaur, Deepak Mishra:
Efficient Framework with Sparse Acquisition in CMOS Image Sensors for Low-Power Edge Devices. iSES 2024: 235-239 - [c17]Bibhudutta Stapathy, Utkarsh Srivastava, Amandeep Kaur:
A Fully Digital Rail-to-Rail Low Power Dynamic Comparator for Smart Devices. iSES 2024: 240-245 - 2023
- [j3]Bibhudutta Satapathy, Amandeep Kaur:
An Energy-efficient and High-speed Dynamic Comparator for Low-noise Applications. Circuits Syst. Signal Process. 42(9): 5108-5120 (2023) - [c16]Sandeep Kodam, Wilfred Kisku, Amandeep Kaur, Deepak Mishra:
On Edge FPN Reduction in CMOS Image Sensor Using CNN with Attention Mechanism. APCCAS 2023: 289-293 - [c15]Wilfred Kisku, Prateek Khandelwal, Amandeep Kaur, Deepak Mishra:
An Intelligent CMOS Image Sensor System Using Edge Information for Image Classification. APCCAS 2023: 314-318 - [c14]Bibhudutta Satapathy, Amandeep Kaur:
A Single Capacitor-Based Offset Reduction Technique for Energy-Efficient Dynamic Comparators. ISCAS 2023: 1-5 - 2022
- [c13]Wilfred Kisku, Mohit Bhushan, Amandeep Kaur, Deepak Mishra:
AI driven Wide Dynamic Range CMOS Image Sensor. AICAS 2022: 366-370 - [c12]Amandeep Kaur, Mukul Sarkar:
An input folding high speed cyclic ADC for column-parallel readout in CMOS image sensors. ISCAS 2022: 910-914 - [c11]Amandeep Kaur:
A Multiplying Digital to Analog Converter Insensitive to Component Mismatch. ISCAS 2022: 1440-1444 - 2021
- [j2]Amandeep Kaur, Deepak Mishra, K. M. Amogh, Mukul Sarkar:
On-Array Compressive Acquisition in CMOS Image Sensors Using Accumulated Spatial Gradients. IEEE Trans. Circuits Syst. Video Technol. 31(2): 523-532 (2021) - [c10]Wilfred Kisku, Amandeep Kaur, Deepak Mishra:
On-chip Pixel Reconstruction using Simple CNN for Sparsely Read CMOS Image Sensor. AICAS 2021: 1-5 - [c9]Bibhudutta Satapathy, Amandeep Kaur:
A High Speed, Low Energy Comparator Based on Current Recycling Approach. ISCAS 2021: 1-5 - [c8]Bibhudutta Satapathy, Amandeep Kaur:
A low kickback noise and low power dynamic comparator. MWSCAS 2021: 146-149 - [c7]Varun Kumar, Bibhudatta Satapathy, Wilfred Kisku, Amandeep Kaur, Deepak Mishra:
CMOS image sensor with adaptive readout scheme for low power applications. MWSCAS 2021: 766-769 - 2020
- [c6]Amandeep Kaur, M. B. Karthik, Mukul Sarkar:
A CMOS Image Sensor with Column-Parallel Cyclic-SAR ADC. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j1]Amandeep Kaur, Deepak Mishra, Mukul Sarkar:
A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 248-252 (2019) - [c5]Amandeep Kaur, Deepak Mishra:
A reconfigurable cyclic ADC for biomedical applications. BioCAS 2019: 1-4 - 2018
- [c4]Amandeep Kaur, Deepak Mishra, Mukul Sarkar:
An On-Chip Interpolation Based Readout Scheme for Low-Power, High-Speed CMOS Image Sensors. IEEE SENSORS 2018: 1-4 - [c3]Amandeep Kaur, Deepak Mishra, Mukul Sarkar:
A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors. ISCAS 2018: 1-5 - 2017
- [c2]Abhishek Shrivastava, Amandeep Kaur, Mukul Sarkar:
A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs. ISOCC 2017: 111-112 - 2016
- [c1]Amandeep Kaur, Mukul Sarkar:
A low power low latency comparator for ramp ADC in CMOS imagers. ISCAS 2016: 1466-1469
Coauthor Index
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last updated on 2026-08-03 05:45 CEST by the dblp team
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