Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.

Jean-Baptiste Cuelle Syed Zahid Ahmed Julien Eydoux Laurent Rouge Jean-Baptiste Cuelle Gilles Sassatelli Lionel Torres Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor. 184-189 2009 DATE https://doi.org/10.1109/DATE.2009.5090655 http://dl.acm.org/citation.cfm?id=1874664 conf/date/2009 db/conf/date/date2009.html#AhmedERCST09 Yoann Guillemenet Syed Zahid Ahmed Lionel Torres Alexandre Martheley Julien Eydoux Jean-Baptiste Cuelle Laurent Rouge Gilles Sassatelli MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs. 18-23 2009 ReConFig https://doi.org/10.1109/ReConFig.2009.25 https://doi.ieeecomputersociety.org/10.1109/ReConFig.2009.25 conf/reconfig/2009 db/conf/reconfig/reconfig2009.html#GuillemenetATMECRS09 Syed Zahid Ahmed Julien Eydoux Yoann Guillemenet Alexandre Martheley Laurent Rouge Gilles Sassatelli Lionel Torres