Leakage Current Fluctuation of On/Off-State Stress in 3 nm Process and its Guard-band Compensation.

Yasumasa Tsukamoto Mitsuhiko Igarashi Yuuki Uchida Keiichiro Iwamoto Yoshio Takazawa Yasumasa Tsukamoto Leakage Current Fluctuation of On/Off-State Stress in 3 nm Process and its Guard-band Compensation. 9 2025 IRPS https://doi.org/10.1109/IRPS48204.2025.10983237 conf/irps/2025 db/conf/irps/irps2025.html#IgarashiUITT25

Mitsuhiko Igarashi Yuuki Uchida Yoshio Takazawa Makoto Yabuuchi Yasumasa Tsukamoto Koji Shibutani Kazutoshi Kobayashi An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM. 1536-1545 2021 104-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 11 https://doi.org/10.1587/transfun.2020kep0017 db/journals/ieiceta/ieiceta104.html#IgarashiUTYTSK21

Makoto Yabuuchi Masao Morimoto Yasumasa Tsukamoto Shinji Tanaka A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier. 1-2 2020 VLSI Circuits https://doi.org/10.1109/VLSICircuits18222.2020.9162775 conf/vlsic/2020 db/conf/vlsic/vlsic2020.html#YabuuchiMTT20 Mitsuhiko Igarashi Yuuki Uchida Yoshio Takazawa Makoto Yabuuchi Yasumasa Tsukamoto Koji Shibutani Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process. 1-6 2019 IRPS https://doi.org/10.1109/IRPS.2019.8720508 conf/irps/2019 db/conf/irps/irps2019.html#IgarashiUTYTS19

Makoto Yabuuchi Yasumasa Tsukamoto Hidehiro Fujiwara Miki Tanaka Shinji Tanaka Koji Nii A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. 2335-2344 2018 26 IEEE Trans. Very Large Scale Integr. Syst. 11 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2864267 db/journals/tvlsi/tvlsi26.html#YabuuchiTFTSN18

Mitsuhiko Igarashi Yuuki Uchida Yoshio Takazawa Yasumasa Tsukamoto Koji Shibutani Koji Nii A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process. 195-196 2018 A-SSCC https://doi.org/10.1109/ASSCC.2018.8579303 conf/asscc/2018 db/conf/asscc/asscc2018.html#IgarashiUTTSN18 Mitsuhiko Igarashi Yuuki Uchida Yoshio Takazawa Yasumasa Tsukamoto Koji Shibutani Koji Nii Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET. 1 2018 IRPS https://doi.org/10.1109/IRPS.2018.8353654 conf/irps/2018 db/conf/irps/irps2018.html#IgarashiUTTSN18 Mitsuhiko Igarashi Yoshio Takazawa Yasumasa Tsukamoto Kan Takeuchi Koji Shibutani NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator. 201-204 2017 A-SSCC https://doi.org/10.1109/ASSCC.2017.8240251 conf/asscc/2017 db/conf/asscc/asscc2017.html#IgarashiTTTS17 Yuichiro Ishii Makoto Yabuuchi Yohei Sawada Masao Morimoto Yasumasa Tsukamoto Yuta Yoshida Ken Shibata Toshiaki Sano Shinji Tanaka Koji Nii A 5.92-Mb/mm<sup>2</sup> 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. 17-20 2016 A-SSCC https://doi.org/10.1109/ASSCC.2016.7844124 conf/asscc/2016 db/conf/asscc/asscc2016.html#IshiiYSMTYSSTN16 Yasumasa Tsukamoto Masao Morimoto Makoto Yabuuchi Miki Tanaka Koji Nii 1.8 Mbit/mm<sup>2</sup> ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology. 274- 2015 VLSIC https://doi.org/10.1109/VLSIC.2015.7231286 conf/vlsic/2015 db/conf/vlsic/vlsic2015.html#TsukamotoMYTN15

Yukiko Umemoto Koji Nii Jiro Ishikawa Makoto Yabuuchi Kazuyoshi Okamoto Yasumasa Tsukamoto Shinji Tanaka Koji Tanaka Tetsuya Matsumura Kazutaka Mori Kazumasa Yanagisawa 28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. 575-584 2014 22 IEEE Trans. Very Large Scale Integr. Syst. 3 https://doi.org/10.1109/TVLSI.2013.2246201 db/journals/tvlsi/tvlsi22.html#UmemotoNIYOTTTMMY14

Makoto Yabuuchi Yasumasa Tsukamoto Masao Morimoto Miki Tanaka Koji Nii 13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. 234-235 2014 ISSCC https://doi.org/10.1109/ISSCC.2014.6757414 conf/isscc/2014 db/conf/isscc/isscc2014.html#YabuuchiTMTN14 Shinji Tanaka Yuichiro Ishii Makoto Yabuuchi Toshiaki Sano Koji Tanaka Yasumasa Tsukamoto Koji Nii Hirotoshi Sato A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. 1-2 2014 VLSIC https://doi.org/10.1109/VLSIC.2014.6858411 conf/vlsic/2014 db/conf/vlsic/vlsic2014.html#TanakaIYSTTNS14

Noriaki Maeda Shigenobu Komatsu Masao Morimoto Koji Tanaka Yasumasa Tsukamoto Koji Nii Yasuhisa Shimazaki A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. 917-923 2013 48 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2012.2237571 db/journals/jssc/jssc48.html#MaedaKMTTNS13

Makoto Yabuuchi Hidehiro Fujiwara Yasumasa Tsukamoto Miki Tanaka Shinji Tanaka Koji Nii A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. 1-4 2013 CICC https://doi.org/10.1109/CICC.2013.6658451 conf/cicc/2013 db/conf/cicc/cicc2013.html#YabuuchiFTTTN13 Koji Nii Makoto Yabuuchi Hidehiro Fujiwara Yasumasa Tsukamoto Yuichiro Ishii Tetsuya Matsumura Yoshio Matsuda A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. 438-441 2013 ISQED https://doi.org/10.1109/ISQED.2013.6523648 conf/isqed/2013 db/conf/isqed/isqed2013.html#NiiYFTIMM13 Koji Nii Yasumasa Tsukamoto Yuichiro Ishii Makoto Yabuuchi Hidehiro Fujiwara Kazuyoshi Okamoto A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. 246-251 2012 Asian Test Symposium https://doi.org/10.1109/ATS.2012.59 https://doi.ieeecomputersociety.org/10.1109/ATS.2012.59 conf/ats/2012 db/conf/ats/ats2012.html#NiiTIYFO12 Yasumasa Tsukamoto Makoto Yabuuchi Hidehiro Fujiwara Koji Nii Changhwan Shin Tsu-Jae King Liu Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. 270-274 2012 ISQED https://doi.org/10.1109/ISQED.2012.6187505 conf/isqed/2012 db/conf/isqed/isqed2012.html#TsukamotoYFNSL12 Takeshi Kida Yasumasa Tsukamoto Yuji Kihara Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis. 572-579 2012 ISQED https://doi.org/10.1109/ISQED.2012.6187551 conf/isqed/2012 db/conf/isqed/isqed2012.html#KidaTK12 Yuichiro Ishii Yasumasa Tsukamoto Koji Nii Hidehiro Fujiwara Makoto Yabuuchi Koji Tanaka Shinji Tanaka Yasuhisa Shimazaki A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. 236-238 2012 ISSCC https://doi.org/10.1109/ISSCC.2012.6176991 conf/isscc/2012 db/conf/isscc/isscc2012.html#IshiiTNFYTTS12 Hidehiro Fujiwara Makoto Yabuuchi Yasumasa Tsukamoto Hirofumi Nakano Toru Owada Hiroyuki Kawai Koji Nii A stable chip-ID generating physical uncloneable function using random address errors in SRAM. 143-147 2012 SoCC https://doi.org/10.1109/SOCC.2012.6398399 conf/socc/2012 db/conf/socc/socc2012.html#FujiwaraYTNOKN12

Yuichiro Ishii Hidehiro Fujiwara Shinji Tanaka Yasumasa Tsukamoto Koji Nii Yuji Kihara Kazumasa Yanagisawa A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. 2535-2544 2011 46 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.2011.2164021 db/journals/jssc/jssc46.html#IshiiFTTNKY11

Yasumasa Tsukamoto Takeshi Kida T. Yamaki Yuichiro Ishii Koji Nii Koji Tanaka Shinji Tanaka Yuji Kihara Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. 1-4 2011 CICC https://doi.org/10.1109/CICC.2011.6055314 conf/cicc/2011 db/conf/cicc/cicc2011.html#TsukamotoKYINTTK11 Makoto Yabuuchi Yasumasa Tsukamoto Hidehiro Fujiwara Shigeki Tawa Koji Maekawa Motoshige Igarashi Koji Nii A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. 285-290 2011 ISLPED http://portal.acm.org/citation.cfm?id=2016868&CFID=34981777&CFTOKEN=25607807 conf/islped/2011 db/conf/islped/islped2011.html#YabuuchiTFTMIN11 Koji Nii Makoto Yabuuchi Yasumasa Tsukamoto Yuuichi Hirano Toshiaki Iwamatsu Yuji Kihara A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. 356-357 2010 ISSCC https://doi.org/10.1109/ISSCC.2010.5433817 conf/isscc/2010 db/conf/isscc/isscc2010.html#NiiYTHIK10

Koji Nii Yasumasa Tsukamoto Makoto Yabuuchi Yasuhiro Masuda Susumu Imaoka Keiichi Usui Shigeki Ohbayashi Hiroshi Makino Hirofumi Shinohara Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. 977-986 2009 44 IEEE J. Solid State Circuits 3 https://doi.org/10.1109/JSSC.2009.2013766 db/journals/jssc/jssc44.html#NiiTYMIUOMS09

Shigeki Ohbayashi Makoto Yabuuchi Kazushi Kono Yuji Oda Susumu Imaoka Keiichi Usui Toshiaki Yonezu Takeshi Iwamoto Koji Nii Yasumasa Tsukamoto Masashi Arakawa Takahiro Uchida Masakazu Okada Atsushi Ishii Tsutomu Yoshihara Hiroshi Makino Koichiro Ishibashi Hirofumi Shinohara A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. 96-108 2008 43 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/JSSC.2007.908004 db/journals/jssc/jssc43.html#OhbayashiYKOIUY08

Koji Nii Makoto Yabuuchi Yasumasa Tsukamoto Shigeki Ohbayashi Susumu Imaoka Hiroshi Makino Yoshinobu Yamagami Satoshi Ishikura Toshio Terano Toshiyuki Oashi Keiji Hashimoto Akio Sebe Gen Okazaki Katsuji Satomi Hironori Akamatsu Hirofumi Shinohara A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. 180-191 2008 43 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/JSSC.2007.907998 db/journals/jssc/jssc43.html#NiiYTOIMYITOHSO08

Satoshi Ishikura Marefusa Kurumada Toshio Terano Yoshinobu Yamagami Naoki Kotani Katsuji Satomi Koji Nii Makoto Yabuuchi Yasumasa Tsukamoto Shigeki Ohbayashi Toshiyuki Oashi Hiroshi Makino Hirofumi Shinohara Hironori Akamatsu A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. 938-945 2008 43 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2008.917568 db/journals/jssc/jssc43.html#IshikuraKTYKSNY08

Shigeki Ohbayashi Makoto Yabuuchi Koji Nii Yasumasa Tsukamoto Susumu Imaoka Yuji Oda Tsutomu Yoshihara Motoshige Igarashi Masahiko Takeuchi Hiroshi Kawashima Yasuo Yamaguchi Kazuhiro Tsukamoto Masahide Inuishi Hiroshi Makino Koichiro Ishibashi Hirofumi Shinohara A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. 820-829 2007 42 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2007.891648 db/journals/jssc/jssc42.html#OhbayashiYNTIOY07

Makoto Yabuuchi Koji Nii Yasumasa Tsukamoto Shigeki Ohbayashi Susumu Imaoka Hiroshi Makino Yoshinobu Yamagami Satoshi Ishikura Toshio Terano Toshiyuki Oashi Keiji Hashimoto Akio Sebe Gen Okazaki Katsuji Satomi Hironori Akamatsu Hirofumi Shinohara A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. 326-606 2007 ISSCC https://doi.org/10.1109/ISSCC.2007.373426 conf/isscc/2007 db/conf/isscc/isscc2007.html#YabuuchiNTOIMYITOHSOSAS07 Shigeki Ohbayashi Makoto Yabuuchi Kazushi Kono Yuji Oda Susumu Imaoka Keiichi Usui Toshiaki Yonezu Takeshi Iwamoto Koji Nii Yasumasa Tsukamoto Masashi Arakawa Takahiro Uchida Masakazu Okada Atsushi Ishii Hiroshi Makino Koichiro Ishibashi Hirofumi Shinohara A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. 488-617 2007 ISSCC https://doi.org/10.1109/ISSCC.2007.373507 conf/isscc/2007 db/conf/isscc/isscc2007.html#OhbayashiYKOIUYINTAUOIMIS07 Yasumasa Tsukamoto Koji Nii Susumu Imaoka Yuji Oda Shigeki Ohbayashi Tomoaki Yoshizawa Hiroshi Makino Koichiro Ishibashi Hirofumi Shinohara Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. 398-405 2005 conf/iccad/2005 ICCAD db/conf/iccad/iccad2005.html#TsukamotoNIOOYMIS05 https://doi.org/10.1109/ICCAD.2005.1560101 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2005.1560101 http://dl.acm.org/citation.cfm?id=1129659 Niichi Itoh Yasumasa Tsukamoto Takeshi Shibagaki Koji Nii Hidehiro Takata Hiroshi Makino A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. 73-76 2005 conf/iscas/2005 ISCAS (1) https://doi.org/10.1109/ISCAS.2005.1464527 db/conf/iscas/iscas2005-1.html#ItohTSNTM05

Koji Nii Yasumasa Tsukamoto Tomoaki Yoshizawa Susumu Imaoka Yoshinobu Yamagami Toshikazu Suzuki Akinori Shibayama Hiroshi Makino Shuhei Iwade A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. 684-693 2004 39 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2004.825235 db/journals/jssc/jssc39.html#NiiTYIYSSMI04

Masato Fujinaga I. Tottori Tatsuya Kunikiyo Tetsuya Uchida Norihiko Kotani Yasumasa Tsukamoto 3-D numerical modeling of thermal flow for insulating thin film using surface diffusion. 631-638 1995 14 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/43.384427 db/journals/tcad/tcad14.html#FujinagaTKUKT95

Hironori Akamatsu Masashi Arakawa Masato Fujinaga Hidehiro Fujiwara Keiji Hashimoto Yuuichi Hirano Mitsuhiko Igarashi Motoshige Igarashi Susumu Imaoka Masahide Inuishi Koichiro Ishibashi Atsushi Ishii Yuichiro Ishii Jiro Ishikawa Satoshi Ishikura Niichi Itoh Shuhei Iwade Toshiaki Iwamatsu Keiichiro Iwamoto Takeshi Iwamoto Hiroyuki Kawai Hiroshi Kawashima Takeshi Kida Yuji Kihara Kazutoshi Kobayashi Shigenobu Komatsu Kazushi Kono Naoki Kotani Norihiko Kotani Tatsuya Kunikiyo Marefusa Kurumada Tsu-Jae King Liu Noriaki Maeda Koji Maekawa Hiroshi Makino Yasuhiro Masuda Yoshio Matsuda Tetsuya Matsumura Kazutaka Mori Masao Morimoto Hirofumi Nakano Koji Nii Toshiyuki Oashi Yuji Oda Shigeki Ohbayashi Masakazu Okada Kazuyoshi Okamoto Gen Okazaki Toru Owada Toshiaki Sano Hirotoshi Sato Katsuji Satomi Yohei Sawada Akio Sebe Takeshi Shibagaki Ken Shibata Akinori Shibayama Koji Shibutani Yasuhisa Shimazaki Changhwan Shin Hirofumi Shinohara Toshikazu Suzuki Hidehiro Takata Yoshio Takazawa Kan Takeuchi Masahiko Takeuchi Koji Tanaka Miki Tanaka Shinji Tanaka Shigeki Tawa Toshio Terano I. Tottori Kazuhiro Tsukamoto Takahiro Uchida Tetsuya Uchida Yuuki Uchida Yukiko Umemoto Keiichi Usui Makoto Yabuuchi Yoshinobu Yamagami Yasuo Yamaguchi T. Yamaki Kazumasa Yanagisawa Toshiaki Yonezu Yuta Yoshida Tsutomu Yoshihara Tomoaki Yoshizawa