An open-loop full CMOS 103 MHz -61 dB THD S/H circuit.

Khayrollah Hadidi Masahiro Sasaki Tadatoshi Watanabe Daigo Muramatsu Takashi Matsumoto 0001 An open-loop full CMOS 103 MHz -61 dB THD S/H circuit. 381-383 1998 CICC https://doi.org/10.1109/CICC.1998.695004 conf/cicc/1998 db/conf/cicc/cicc1998.html#HadidiSWMM98