An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs.

Paolo Zicari Pasquale Corsonello Stefania Perri An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs. 168-171 2006 ICECS https://doi.org/10.1109/ICECS.2006.379746 conf/icecsys/2006 db/conf/icecsys/icecsys2006.html#ZicariCP06