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"Layout engineering to suppress hysteresis of negative capacitance FinFET."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Eunah Ko et al. (2017)

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DOI: 10.1109/ICICDT.2017.7993498

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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  dblp key:
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  - https://dblp.org/rec/conf/icicdt/KoJSN17
Eunah Ko, Jaesung Jo, Changhwan Shin, Bich-Yen Nguyen:
Layout engineering to suppress hysteresis of negative capacitance FinFET. ICICDT 2017: 1-3

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