Toxicbias-reasoning: a multicultural dataset for social bias detection with human-aligned reasoning.

Virendra Singh

Anuj Kumar Mahendra Kumar Gurve Satyadev Ahlawat Yamuna Prasad Virendra Singh Toxicbias-reasoning: a multicultural dataset for social bias detection with human-aligned reasoning. 2026 June 35 60 Lang. Resour. Evaluation 2 https://doi.org/10.1007/s10579-026-09916-w db/journals/lre/lre60.html#KumarGAPS26 streams/journals/lre

Anuj Kumar Satyadev Ahlawat Yamuna Prasad Virendra Singh Revisiting Evaluation of Question Answering Systems in Low-Resource Indic Languages: Bridging Human and Metric Alignment. 703-718 2026 ACL (2) https://doi.org/10.18653/v1/2026.acl-short.58 https://aclanthology.org/2026.acl-short.58/ conf/acl/2026-2 db/conf/acl/acl2026-2.html#KumarAPS26 Munawira Kotyad Yashvardhan Rathore Ganesh Sai Shanmukhi Virendra Singh FlIP: Flow-Based Instruction Processing for Out-of-Order Scheduling in GPGPUs. 20-28 2026 CF https://doi.org/10.1145/3801487.3801823 conf/cf/2026 db/conf/cf/cf2026.html#KotyadRSS26 Munawira Kotyad Ganesh Sai Shanmukhi Yashvardhan Rathore Virendra Singh POSTER: Bypassing Blocking Instructions to enable Out-Of-Order Execution in GPGPUs. 337-338 2026 CF https://doi.org/10.1145/3801487.3805607 conf/cf/2026 db/conf/cf/cf2026.html#KotyadSRS26 Sonali Shukla Govind Rajhans Jadhav Durgesh Sardan Suryakant Toraskar Jaynarayan T. Tudu Makoto Ikeda Masahiro Fujita 0004 Virendra Singh A SAT-Hard Compound Logic Locking Scheme with Empirical Resistance to Known Structural Attacks. DDECS 2026 1-6 conf/ddecs/2026 https://doi.org/10.1109/DDECS69233.2026.11520982 db/conf/ddecs/ddecs2026.html#ShuklaJSTTIFS26 streams/conf/ddecs Tejeshwar Bhagatsing Thorawade Varun Venkitaraman Keerthisagar Kokkiligadda Samiksha Verma Virendra Singh Vtrack: Defending Against All Rowhammer Attack Patterns by Tracking Victim Rows. HOST 2026 12-22 conf/host/2026 https://doi.org/10.1109/HOST68814.2026.11604817 db/conf/host/host2026.html#ThorawadeVKVS26 streams/conf/host Samiksha Verma Virendra Singh Beyond Defense: A Rowhammer Mitigation That Boosts Performance. HOST 2026 394-404 conf/host/2026 https://doi.org/10.1109/HOST68814.2026.11604932 db/conf/host/host2026.html#VermaS26 streams/conf/host Veerendrababu Vakkapatla Shariq Faraz Virendra Singh Sparse Rewards as Preferences: Investigating Reward Shaping with Preference-Based RL Methods in Sparse Reward Domains. 244-251 2026 ICAART (1) https://doi.org/10.5220/0014221600004052 conf/icaart/2026-1 db/conf/icaart/icaart2026-1.html#VakkapatlaFS26 Mandru Suma Sri Uddhav Narayan Gilda Tarun Bisht Virendra Singh DREAM: Dynamic, Reinforced, and Evasive Attack Model on Spatio-Temporal GNNs. 2711-2719 2026 ICAART (3) https://doi.org/10.5220/0014316400004052 conf/icaart/2026-3 db/conf/icaart/icaart2026-3.html#SriGBS26 Avinash Kumar Virendra Singh Supratim Biswas Continuation-Preserving Tiling for Pointer-Chasing Optimization in Structured Mutual Recursion. 106-118 2026 ICS https://doi.org/10.1145/3797905.3807858 conf/ics/2026 db/conf/ics/ics2026.html#KumarSB26 Rohit Badjatya Jaydev Bapat Makoto Ikeda Masahiro Fujita 0004 Virendra Singh LPCG: A Capture Activity-Aware Technique for Low-Power Scan Testing. LATS 2026 1-6 conf/latw/2026 https://doi.org/10.1109/LATS70329.2026.11480289 db/conf/latw/lats2026.html#BadjatyaBIFS26 streams/conf/latw Rohit Badjatya Harsh Gupta Makoto Ikeda Masahiro Fujita 0004 Virendra Singh LA-SCG: Layout-Aware Scan Chain Grouping for Peak Shift Power and IR-Drop Mitigation in Scan-Based Testing. LATS 2026 1-6 conf/latw/2026 https://doi.org/10.1109/LATS70329.2026.11480375 db/conf/latw/lats2026.html#BadjatyaGIFS26 streams/conf/latw Tejeshwar Bhagatsing Thorawade Rishab Ravi Varun Venkitaraman Keerthisagar Kokkiligadda Nirmal Kumar Boran Virendra Singh SPARTON: Secure Dynamic Partition Scheme for Last-Level Cache. 517-528 2026 SECRYPT (1) https://doi.org/10.5220/0015053000004103 conf/secrypt/2026-1 db/conf/secrypt/secrypt2026-1.html#ThorawadeRVKBS26

Jitendra Kumar Samriya Virendra Singh Gourav Bathla Meena Malik Varsha Arya Wadee Alhalabi Brij B. Gupta Enhancing Healthcare Data Privacy in Cloud IoT Networks Using Anomaly Detection and Optimization with Explainable AI (ExAI). 2025 3893-3910 84 Comput. Mater. Continua 2 https://doi.org/10.32604/cmc.2025.063242 db/journals/cmc/cmc84.html#SamriyaSBMAAG25 streams/journals/cmc

Aditi Gupta Adeiza James Onumanyi Satyadev Ahlawat Yamuna Prasad Virendra Singh B-CAVE: A Robust Online Time Series Change Point Detection Algorithm Based on the Between-Class Average and Variance Evaluation Approach. 75-88 2025 January 37 IEEE Trans. Knowl. Data Eng. 1 https://doi.org/10.1109/TKDE.2024.3492339 db/journals/tkde/tkde37.html#GuptaOAPS25 streams/journals/tkde

Rohit Badjatya Kapil Sharma Makoto Ikeda Masahiro Fujita 0004 Virendra Singh Weight-Aware Scan Chain Stitching for Shift Power Minimization under Routing Constraints. ATS 2025 7-12 conf/ats/2025 https://doi.org/10.1109/ATS66998.2025.00010 db/conf/ats/ats2025.html#BadjatyaSIFS25 streams/conf/ats Pinaki Das Virendra Singh Pushpak Bhattacharyya Gholamreza Haffari Video-guided Machine Translation: A Survey of Models, Datasets, and Challenges. IJCNLP-AACL (long papers) 2025 3346-3356 conf/ijcnlp/2025-l https://doi.org/10.18653/v1/2025.ijcnlp-long.178 https://aclanthology.org/2025.ijcnlp-long.178/ db/conf/ijcnlp/ijcnlp2025-l.html#DasSBH25 streams/conf/ijcnlp Raghunandana K. K Yogesh Prasad K. R Matteo Sonza Reorda Virendra Singh GPD: Predictive Control Flow Error Detection Leveraging Data Flow Error Detection Methods. 1-5 2025 IOLTS https://doi.org/10.1109/IOLTS65288.2025.11116971 conf/iolts/2025 db/conf/iolts/iolts2025.html#KRRS25 streams/conf/iolts Anjum Riaz Gaurav Kumar 0001 Yamuna Prasad Satyadev Ahlawat Virendra Singh A New Hardware Trojan Attack on Scan-obfuscated Logic-locked Circuits. 1-5 2025 ISCAS https://doi.org/10.1109/ISCAS56072.2025.11043737 conf/iscas/2025 db/conf/iscas/iscas2025.html#RiazKPAS25 Varun Venkitaraman Shrasti Bhargava Tejeshwar Bhagatsing Thorawade Keerthisagar Kokkiligadda Rahul Kumar Virendra Singh RRR: Robust runtime reconfigurable shared cache management scheme for GPGPUs. 1-5 2025 ISCAS https://doi.org/10.1109/ISCAS56072.2025.11044103 conf/iscas/2025 db/conf/iscas/iscas2025.html#VenkitaramanBTK25 Jaidev Shenoy Virendra Singh Kelly Ockunzzi Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time. 588-598 2025 ITC https://doi.org/10.1109/ITC58126.2025.00095 conf/itc/2025 db/conf/itc/itc2025.html#ShenoySO25 streams/conf/itc Samiksha Verma Virendra Singh TRAP: Time-Aware Probabilistic In-Dram RowHammer Solution. 1-11 2025 SBAC-PAD https://doi.org/10.1109/SBAC-PAD66369.2025.00034 conf/sbac-pad/2025 db/conf/sbac-pad/sbac-pad2025.html#VermaS25 streams/conf/sbac-pad Varun Venkitaraman Rishab Ravi Tejeshwar Bhagatsing Thorawade Nirmal Kumar Boran Virendra Singh SCAM: Secure Shared Cache Partitioning Scheme to Enhance Throughput of CMPs. 144-155 2025 SECRYPT https://doi.org/10.5220/0013518700003979 conf/secrypt/2025 db/conf/secrypt/secrypt2025.html#VenkitaramanRTB25 Nikhil Kumar Parida Sarath Babu 0003 Neeraj Panwar Virendra Singh EDQKD: Enhanced-Dynamic Quantum Key Distributions with Improved Security and Key Rate. 586-591 2025 SECRYPT https://doi.org/10.5220/0013507900003979 conf/secrypt/2025 db/conf/secrypt/secrypt2025.html#Parida0PS25 Rushikesh Kawale Sarath Babu 0003 Virendra Singh Stegoslayer: A Robust Browser-Integrated Approach for Thwarting Stegomalware. 601-606 2025 SECRYPT https://doi.org/10.5220/0013509200003979 conf/secrypt/2025 db/conf/secrypt/secrypt2025.html#Kawale0S25 Prokash Ghosh Gaurav Kumar 0001 Sohan Lal Satyadev Ahlawat Virendra Singh On Enhancing the Security Against Memory Disclosure Attacks. 1-6 2025 SOCC https://doi.org/10.1109/SOCC66126.2025.11235448 conf/socc/2025 db/conf/socc/socc2025.html#GhoshKLAS25 streams/conf/socc Varun Venkitaraman Tejeshwar Bhagatsing Thorawade Mitul Tandon Keerthisagar Kokkiligadda Virendra Singh Janak Patel LiC: Low-Cost Cache Replacement Algorithm for All Cache Levels. VLSI-SoC 2025 1-5 conf/vlsi/2025 https://doi.org/10.1109/VLSI-SoC64688.2025.11421757 db/conf/vlsi/vlsisoc2025.html#VenkitaramanTTKSP25 streams/conf/vlsi Prakhar Diwan Nirmal Kumar Boran Virendra Singh Lichen: Leveraging Coupled Heterogeneity. 19-24 2025 VLSID https://doi.org/10.1109/VLSID64188.2025.00017 conf/vlsid/2025 db/conf/vlsid/vlsid2025.html#DiwanBS25

Virendra Singh Mahendra Pratap Singh Saumya Hegde Maanak Gupta Security in 5G Network Slices: Concerns and Opportunities. 52727-52743 2024 12 IEEE Access https://doi.org/10.1109/ACCESS.2024.3386632 db/journals/access/access12.html#SinghSHG24

Aditi Gupta Sukanya Gupta Adeiza James Onumanyi Satyadev Ahlawat Yamuna Prasad Virendra Singh A-TSPD: autonomous-two stage algorithm for robust peak detection in online time series. 4063-4076 2024 July 27 Clust. Comput. 4 https://doi.org/10.1007/s10586-024-04369-8 db/journals/cluster/cluster27.html#GuptaGOAPS24 streams/journals/cluster

Sarath Babu 0003 Virendra Singh BD-MDLC: Behavior description-based enhanced malware detection for windows environment using longformer classifier. 104031 2024 146 Comput. Secur. https://doi.org/10.1016/j.cose.2024.104031 db/journals/compsec/compsec146.html#BabuS24 streams/journals/compsec

Winnie Thomas Virendra Singh Accelerating Neural Network Inference in Handwritten Digit Recognition - Comparative Study. 2430001:1-2430001:16 2024 September & December 34 Parallel Process. Lett. 3&4 https://doi.org/10.1142/S0129626424300010 db/journals/ppl/ppl34.html#ThomasS24 streams/journals/ppl

Aditi Gupta Adeiza James Onumanyi Satyadev Ahlawat Yamuna Prasad Virendra Singh Adnan M. Abu-Mahfouz DAT: A robust Discriminant Analysis-based Test of unimodality for unknown input distributions. 125-132 2024 182 Pattern Recognit. Lett. https://doi.org/10.1016/j.patrec.2024.04.021 db/journals/prl/prl182.html#GuptaOAPSA24

Raghunandana K. K Yogesh Prasad K. R Matteo Sonza Reorda Virendra Singh TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. 104-109 2024 DDECS https://doi.org/10.1109/DDECS60919.2024.10508915 conf/ddecs/2024 db/conf/ddecs/ddecs2024.html#KRRS24 Rohit Badjatya N. S. Vinay Rahul Kumar Jaynarayan T. Tudu Masahiro Fujita 0004 Virendra Singh Physical-Design Aware Scan Cell Reordering for Low Power Testing. 1-6 2024 EWDTS https://doi.org/10.1109/EWDTS63723.2024.10873686 conf/ewdts/2024 db/conf/ewdts/ewdts2024.html#BadjatyaVKTFS24 Raghunandana K. K Yogesh Prasad K. R Matteo Sonza Reorda Virendra Singh TRRR: Accelerated Online Error Detecting and Correcting Fault Tolerant Architecture. 1-6 2024 EWDTS https://doi.org/10.1109/EWDTS63723.2024.10873630 conf/ewdts/2024 db/conf/ewdts/ewdts2024.html#KRRS24 Nirmal Kumar Boran Prakhar Diwan Meet Udeshi Shubhankit Rathore Virendra Singh HIDC: Heterogeneous-ISA Dynamic Core. 284-291 2024 HPCC https://doi.org/10.1109/HPCC64274.2024.00047 conf/hpcc/2024 db/conf/hpcc/hpcc2024.html#BoranDURS24 Chandramani Chaudhary Nirmal Kumar Boran N. Sangeeth Virendra Singh GNNDLD: Graph Neural Network with Directional Label Distribution. 165-176 2024 ICAART (2) https://doi.org/10.5220/0012321400003636 conf/icaart/2024-2 db/conf/icaart/icaart2024-2.html#ChaudharyBSS24 Mandru Suma Sri Chakka Srikanth Yadav Tikaram Sanyashi Virendra Singh MALAI: ML-Based Attack on Learning with Error Problem. 404-421 2024 ICISS https://doi.org/10.1007/978-3-031-80020-7_23 conf/iciss/2024 db/conf/iciss/iciss2024.html#SriYSS24 streams/conf/iciss Samiksha Verma Virendra Singh SMS: Solving Many-sided RowHammer. 78-88 2024 MEMSYS https://doi.org/10.1145/3695794.3695802 conf/memsys/2024 db/conf/memsys/memsys2024.html#VermaS24 Tejeshwar Bhagatsing Thorawade Prajakta Yeola Varun Venkitaraman Virendra Singh S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks. 218-228 2024 SBAC-PAD https://doi.org/10.1109/SBAC-PAD63648.2024.00027 conf/sbac-pad/2024 db/conf/sbac-pad/sbac-pad2024.html#ThorawadeYVS24 streams/conf/sbac-pad Tarun Bisht Sarath Babu 0003 Virendra Singh Critical Behavior Sequence Monitoring for Early Malware Detection. 1-8 2024 SIN https://doi.org/10.1109/SIN63213.2024.10871779 conf/sin/2024 db/conf/sin/sin2024.html#Bisht0S24 Prakhar Diwan Suryakant Toraskar Varun Venkitaraman Nirmal Kumar Boran Chandramani Chaudhary Virendra Singh MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures. 348-353 2024 VLSID https://doi.org/10.1109/VLSID60093.2024.00064 conf/vlsid/2024 db/conf/vlsid/vlsid2024.html#DiwanTVBCS24 Raj Kumar Choudhary Janeel Patel Virendra Singh Early Execution for Soft Error Detection. 366-371 2024 VLSID https://doi.org/10.1109/VLSID60093.2024.00067 conf/vlsid/2024 db/conf/vlsid/vlsid2024.html#ChoudharyPS24 Gowthami Konganapalle Sonali Shukla Virendra Singh SMASh: A State Encoding Methodology Against Attacks on Finite State Machines. 1-6 2023 ATS https://doi.org/10.1109/ATS59501.2023.10318015 conf/ats/2023 db/conf/ats/ats2023.html#KonganapalleSS23 Govind Rajhans Jadhav Sonali Shukla Virendra Singh On Attacking Scan-based Logic Locking Schemes. 1-4 2023 DFT https://doi.org/10.1109/DFT59622.2023.10313561 conf/dft/2023 db/conf/dft/dft2023.html#JadhavSS23 Raghunandana K. K Yogesh Prasad K. R Matteo Sonza Reorda Virendra Singh DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. 1-6 2023 DFT https://doi.org/10.1109/DFT59622.2023.10313543 conf/dft/2023 db/conf/dft/dft2023.html#KRRS23 Tikaram Sanyashi Nirmal Kumar Boran Virendra Singh Secure KNN Computation on Cloud. 197-216 2023 ICISS https://doi.org/10.1007/978-3-031-49099-6_12 conf/iciss/2023 db/conf/iciss/iciss2023.html#SanyashiBS23 Raj Kumar Choudhary Janeel Patel Virendra Singh ERrOR: Improving Performance and Fault Tolerance Using Early Execution. 1-3 2023 IOLTS https://doi.org/10.1109/IOLTS59296.2023.10224863 conf/iolts/2023 db/conf/iolts/iolts2023.html#ChoudharyPS23 Prokash Ghosh Yogesh Gholap Virendra Singh On-Chip SRAM Disclosure Attack Prevention Technique for SoC. 1-7 2023 IOLTS https://doi.org/10.1109/IOLTS59296.2023.10224860 conf/iolts/2023 db/conf/iolts/iolts2023.html#GhoshGS23 Raghunandana K. K B. K. S. V. L. Varaprasad Matteo Sonza Reorda Virendra Singh TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. 1-7 2023 IOLTS https://doi.org/10.1109/IOLTS59296.2023.10224865 conf/iolts/2023 db/conf/iolts/iolts2023.html#KVRS23 Pooja Choudhary Lava Bhargava G. U. Vinod Ashok Kumar Suhag Masahiro Fujita 0004 Virendra Singh Optimization of Imprecise Multiplier Circuits by using Binary Decision Diagram. 115-120 2023 iSES https://doi.org/10.1109/iSES58672.2023.00033 conf/ises/2023 db/conf/ises/ises2023.html#ChoudharyBVSFS23 Pooja Choudhary Lava Bhargava Masahiro Fujita 0004 Virendra Singh LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error. 1-2 2023 LATS https://doi.org/10.1109/LATS58125.2023.10154494 conf/latw/2023 db/conf/latw/lats2023.html#ChoudharyBFS23 Sonali Shukla Bhavika Ranjeet Kumar Virendra Singh SSSN: Secured Streaming Scan Network. 1-6 2023 LATS https://doi.org/10.1109/LATS58125.2023.10154483 conf/latw/2023 db/conf/latw/lats2023.html#ShuklaKS23 Aditi Gupta Adeiza James Onumanyi Satyadev Ahlawat Yamuna Prasad Virendra Singh TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm. 91-97 2023 SOSE https://doi.org/10.1109/SOSE58276.2023.00017 conf/sose/2023 db/conf/sose/sose2023.html#GuptaOAPS23

Pooja Choudhary Lava Bhargava Masahiro Fujita 0004 Virendra Singh Ashok Kumar Suhag Approximating Arithmetic Circuits for IoT Devices Data Processing. 108792 2022 174 Comput. Ind. Eng. https://doi.org/10.1016/j.cie.2022.108792 db/journals/candie/candie174.html#ChoudharyBFSS22

Raghunandana K. K B. K. S. V. L. Varaprasad Matteo Sonza Reorda Virendra Singh REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. 394-397 2022 ISVLSI https://doi.org/10.1109/ISVLSI54635.2022.00088 conf/isvlsi/2022 db/conf/isvlsi/isvlsi2022.html#KVRS22 Nirmal Kumar Boran Pranil Joshi Virendra Singh PASS-P: Performance and Security Sensitive Dynamic Cache Partitioning. 443-450 2022 SECRYPT https://doi.org/10.5220/0011336900003283 conf/secrypt/2022 db/conf/secrypt/secrypt2022.html#BoranJS22 Anishetti Venkatesh Chandan Kumar Jha 0001 G. U. Vinod Masahiro Fujita 0004 Virendra Singh Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. 397-407 2022 VDAT https://doi.org/10.1007/978-3-031-21514-8_33 conf/vdat/2022 db/conf/vdat/vdat2022.html#VenkateshJVFS22 Pooja Choudhary Lava Bhargava Masahiro Fujita 0004 Virendra Singh Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. 435-449 2022 VDAT https://doi.org/10.1007/978-3-031-21514-8_36 conf/vdat/2022 db/conf/vdat/vdat2022.html#ChoudharyBFS22 Ashwin Sanjay Lele Srivatsava Jandhyala Saurabh Gangurde Virendra Singh Sreenivas Subramoney Udayan Ganguly Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache. 499-512 2022 VDAT https://doi.org/10.1007/978-3-031-21514-8_41 conf/vdat/2022 db/conf/vdat/vdat2022.html#LeleJGSSG22 Riccardo Cantoro Francesco Garau Riccardo Masante Sandro Sartoni Virendra Singh Matteo Sonza Reorda Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. 1-7 2022 VTS https://doi.org/10.1109/VTS52500.2021.9794219 conf/vts/2022 db/conf/vts/vts2022.html#CantoroGMSSR22

Nirmal Kumar Boran Shubhankit Rathore Meet Udeshi Virendra Singh Fine-Grained Scheduling in Heterogeneous-ISA Architectures. 9-12 2021 20 IEEE Comput. Archit. Lett. 1 https://doi.org/10.1109/LCA.2020.3045056 db/journals/cal/cal20.html#BoranRUS21

Arindam Sarkar Newton Singh Varun Venkitaraman Virendra Singh DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches. 62-65 2021 20 IEEE Comput. Archit. Lett. 1 https://doi.org/10.1109/LCA.2021.3071717 db/journals/cal/cal20.html#SarkarSVS21

Jaynarayan T. Tudu Satyadev Ahlawat Sonali Shukla Virendra Singh A Framework for Configurable Joint-Scan Design-for-Test Architecture. 593-611 2021 37 J. Electron. Test. 5 https://doi.org/10.1007/s10836-021-05978-6 db/journals/et/et37.html#TuduASS21

V. S. Vineesh Binod Kumar 0001 Rushikesh Shinde Neelam Sharma Masahiro Fujita 0004 Virendra Singh Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. 985-998 2021 40 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/TCAD.2020.3011039 db/journals/tcad/tcad40.html#VineeshKSSFS21

Insha Amin Deepak Mishra 0001 Ravikant Saini Virendra Singh Secrecy Rate Maximization at Near User in Untrusted NOMA with Trusted DF Relay. 1-6 2021 ANTS https://doi.org/10.1109/ANTS52808.2021.9936920 conf/IEEEants/2021 db/conf/IEEEants/IEEEants2021.html#AminMSS21 Abhinish Anand Winnie Thomas Suryakant Toraskar Virendra Singh Predictive Warp Scheduling for Efficient Execution in GPGPU. 295-300 2021 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/3453688.3461525 conf/glvlsi/2021 db/conf/glvlsi/glvlsi2021.html#AnandTTS21 Winnie Thomas Suryakant Toraskar Virendra Singh Dynamic Optimizations in GPU Using Roofline Model. 1-5 2021 ISCAS https://doi.org/10.1109/ISCAS51556.2021.9401255 conf/iscas/2021 db/conf/iscas/iscas2021.html#ThomasTS21 Harsh Bhargav Vineesh V. S. Binod Kumar 0001 Virendra Singh Enhancing Testbench Quality via Genetic Algorithm. 652-656 2021 MWSCAS https://doi.org/10.1109/MWSCAS47672.2021.9531876 conf/mwscas/2021 db/conf/mwscas/mwscas2021.html#BhargavSKS21

Vedant Satav Virendra Singh Locality-based Graph Reordering for Processing Speed-Ups and Impact of Diameter. 2021 abs/2111.12281 CoRR https://arxiv.org/abs/2111.12281 db/journals/corr/corr2111.html#abs-2111-12281

Newton Virendra Singh Trevor E. Carlson PIM-GraphSCC: PIM-Based Graph Processing Using Graph's Community Structures. 151-154 2020 19 IEEE Comput. Archit. Lett. 2 https://doi.org/10.1109/LCA.2020.3039498 db/journals/cal/cal19.html#NewtonSC20

Binod Kumar 0001 Kanad Basu Masahiro Fujita 0004 Virendra Singh Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. 248-261 2020 39 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/TCAD.2018.2883899 https://www.wikidata.org/entity/Q128869022 db/journals/tcad/tcad39.html#KumarBFS20

Binod Kumar 0001 Jay Adhaduk Kanad Basu Masahiro Fujita 0004 Virendra Singh A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. 1002-1015 2020 28 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2019.2958989 db/journals/tvlsi/tvlsi28.html#KumarABFS20

Vinod G. U Vineesh V. S. Jaynarayan T. Tudu Masahiro Fujita 0004 Virendra Singh LUT-based Circuit Approximation with Targeted Error Guarantees. 1-6 2020 ATS https://doi.org/10.1109/ATS49688.2020.9301574 conf/ats/2020 db/conf/ats/ats2020.html#USTFS20 Antara Ganguly Shankar Balachandran Anant V. Nori Virendra Singh Sreenivas Subramoney Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. 121-122 2020 ISPASS https://doi.org/10.1109/ISPASS48437.2020.00026 conf/ispass/2020 db/conf/ispass/ispass2020.html#GangulyBNSS20 Binod Kumar 0001 Swapniel Thakur Kanad Basu Masahiro Fujita 0004 Virendra Singh A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. 101-106 2020 VLSID https://doi.org/10.1109/VLSID49098.2020.00035 conf/vlsid/2020 db/conf/vlsid/vlsid2020.html#0001TBFS20

Binod Kumar 0001 Masahiro Fujita 0004 Virendra Singh SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. 655-678 2019 35 J. Electron. Test. 5 https://doi.org/10.1007/s10836-019-05830-y db/journals/et/et35.html#KumarFS19

Shoba Gopalakrishnan Virendra Singh Soft-error reliable architecture for future microprocessors. 233-242 2019 13 IET Comput. Digit. Tech. 3 https://doi.org/10.1049/iet-cdt.2018.5015 db/journals/iet-cdt/iet-cdt13.html#GopalakrishnanS19

Binod Kumar 0001 Atul Kumar Bhosale Masahiro Fujita 0004 Virendra Singh Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. 99-104 2019 ATS https://doi.org/10.1109/ATS47505.2019.00019 conf/ats/2019 db/conf/ats/ats2019.html#0001BFS19 Vineesh V. S. Binod Kumar 0001 Rushikesh Shinde Akshay Jaiswal Harsh Bhargava Virendra Singh Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. 123-128 2019 ATS https://doi.org/10.1109/ATS47505.2019.00023 conf/ats/2019 db/conf/ats/ats2019.html#S0SJBS19 Satyadev Ahlawat Jaynarayan T. Tudu Manoj Singh Gaur Masahiro Fujita 0004 Virendra Singh Preventing Scan Attack through Test Response Encryption. 1-6 2019 DFT https://doi.org/10.1109/DFT.2019.8875355 conf/dft/2019 db/conf/dft/dft2019.html#AhlawatTGFS19 Raj Kumar Choudhary Newton Singh Harideep Nair Rishabh Rawat Virendra Singh Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency. 702-705 2019 ICCD https://doi.org/10.1109/ICCD46524.2019.00103 conf/iccd/2019 db/conf/iccd/iccd2019.html#ChoudharySNRS19 Satyadev Ahlawat Kailash Ahirwar Jaynarayan T. Tudu Masahiro Fujita 0004 Virendra Singh Securing Scan through Plain-text Restriction. 251-252 2019 IOLTS https://doi.org/10.1109/IOLTS.2019.8854411 conf/iolts/2019 db/conf/iolts/iolts2019.html#AhlawatATFS19 Antara Ganguly Rajeev Muralidhar Virendra Singh Towards Energy Efficient non-von Neumann Architectures for Deep Learning. 335-342 2019 ISQED https://doi.org/10.1109/ISQED.2019.8697354 conf/isqed/2019 db/conf/isqed/isqed2019.html#GangulyMS19 Jaidev Shenoy Kelly Ockunzzi Virendra Singh Kushal Kamal On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. 106-111 2019 VLSID https://doi.org/10.1109/VLSID.2019.00037 conf/vlsid/2019 db/conf/vlsid/vlsid2019.html#ShenoyOSK19 Binod Kumar 0001 Masahiro Fujita 0004 Virendra Singh A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. 389-394 2019 VLSID https://doi.org/10.1109/VLSID.2019.00085 conf/vlsid/2019 db/conf/vlsid/vlsid2019.html#0001FS19 Sukumar Nandi Devesh Jinwala Virendra Singh Vijay Laxmi Manoj Singh Gaur Parvez Faruki Security and Privacy - Second ISEA International Conference, ISEA-ISAP 2018, Jaipur, India, January, 9-11, 2019, Revised Selected Papers ISEA-ISAP Springer 2019 Communications in Computer and Information Science 939 978-981-13-7560-6 978-981-13-7561-3 https://doi.org/10.1007/978-981-13-7561-3 db/conf/iseaisap/iseaisap2018.html S. Rajaram 0001 N. B. Balamurugan D. Gracia Nirmala Rani Virendra Singh VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers VDAT Springer 2019 Communications in Computer and Information Science 892 978-981-13-5949-1 978-981-13-5950-7 https://doi.org/10.1007/978-981-13-5950-7 db/conf/vdat/vdat2018.html Anirban Sengupta Sudeb Dasgupta Virendra Singh Rohit Sharma Santosh Kumar Vishvakarma VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers VDAT Springer 2019 Communications in Computer and Information Science 1066 978-981-32-9766-1 978-981-32-9767-8 https://doi.org/10.1007/978-981-32-9767-8 db/conf/vdat/vdat2019.html

Toral Shah Anzhela Yu. Matrosova Masahiro Fujita 0004 Virendra Singh Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. 53-65 2018 34 J. Electron. Test. 1 https://doi.org/10.1007/s10836-018-5703-3 db/journals/et/et34.html#ShahMFS18

Rohini Gulve Virendra Singh ATPG power guards: On limiting the test power below threshold. 301-304 2018 DATE https://doi.org/10.23919/DATE.2018.8342025 conf/date/2018 db/conf/date/date2018.html#GulveS18 Satyadev Ahlawat Darshit Vaghani Naveen Bazard Virendra Singh Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks. 1-6 2018 EWDTS https://doi.org/10.1109/EWDTS.2018.8524752 conf/ewdts/2018 db/conf/ewdts/ewdts2018.html#AhlawatVBS18 Suhit Pai Newton Singh Virendra Singh AB-Aware: Application Behavior Aware Management of Shared Last Level Caches. 237-242 2018 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/3194554.3194573 conf/glvlsi/2018 db/conf/glvlsi/glvlsi2018.html#PaiSS18 Binod Kumar 0001 Kanad Basu Virendra Singh A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. 1-8 2018 IGSC https://doi.org/10.1109/IGCC.2018.8752141 conf/green/2018 db/conf/green/green2018.html#0001BS18 Sandeep Goyal Ron Joseph Virendra Singh Shalabh Gupta A PAM-4 10S/12S line coding scheme with equi-probable levels. 1-5 2018 ISCAS https://doi.org/10.1109/ISCAS.2018.8351148 conf/iscas/2018 db/conf/iscas/iscas2018.html#GoyalJSG18 Nihar Hage Satyadev Ahlawat Virendra Singh In-situ Monitoring for Slack Time Violation Without Performance Penalty. 1-5 2018 ISCAS https://doi.org/10.1109/ISCAS.2018.8351000 conf/iscas/2018 db/conf/iscas/iscas2018.html#HageAS18 Darshit Vaghani Satyadev Ahlawat Jaynarayan T. Tudu Masahiro Fujita 0004 Virendra Singh On Securing Scan Design Through Test Vector Encryption. 1-5 2018 ISCAS https://doi.org/10.1109/ISCAS.2018.8351212 conf/iscas/2018 db/conf/iscas/iscas2018.html#VaghaniATFS18 Ankit Jindal Binod Kumar 0001 Nitish Jindal Masahiro Fujita 0004 Virendra Singh Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. 46-51 2018 ISVLSI https://doi.org/10.1109/ISVLSI.2018.00019 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2018.00019 conf/isvlsi/2018 db/conf/isvlsi/isvlsi2018.html#Jindal0JFS18 Antara Ganguly Virendra Singh Rajeev Muralidhar Masahiro Fujita 0004 Memory-system requirements for convolutional neural networks. 291-197 2018 MEMSYS https://doi.org/10.1145/3240302.3240427 https://www.wikidata.org/entity/Q130970887 conf/memsys/2018 db/conf/memsys/memsys2018.html#GangulySMF18

Ankush Srivastava Virendra Singh Adit D. Singh Kewal K. Saluja A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. 721-739 2017 33 J. Electron. Test. 6 https://doi.org/10.1007/s10836-017-5692-7 db/journals/et/et33.html#SrivastavaSSS17

Satyadev Ahlawat Darshit Vaghani Jaynarayan T. Tudu Virendra Singh On Securing Scan Design from Scan-Based Side-Channel Attacks. 58-63 2017 ATS https://doi.org/10.1109/ATS.2017.23 https://doi.ieeecomputersociety.org/10.1109/ATS.2017.23 conf/ats/2017 db/conf/ats/ats2017.html#AhlawatVTS17 Satyadev Ahlawat Darshit Vaghani Virendra Singh Preventing scan-based side-channel attacks through key masking. 1-4 2017 DFT https://doi.org/10.1109/DFT.2017.8244434 https://doi.ieeecomputersociety.org/10.1109/DFT.2017.8244434 conf/dft/2017 db/conf/dft/dft2017.html#AhlawatVS17 Shoba Gopalakrishnan Virendra Singh REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture. 1-6 2017 DFT https://doi.org/10.1109/DFT.2017.8244454 https://doi.ieeecomputersociety.org/10.1109/DFT.2017.8244454 conf/dft/2017 db/conf/dft/dft2017.html#GopalakrishnanS17 Satyadev Ahlawat Darshit Vaghani Virendra Singh An efficient test technique to prevent scan-based side-channel attacks. 1-2 2017 ETS https://doi.org/10.1109/ETS.2017.7968241 conf/ets/2017 db/conf/ets/ets2017.html#AhlawatVS17 Rohini Gulve Anshu Goel Virendra Singh PHP: Power hungry pattern generation at higher abstraction level. 1-4 2017 EWDTS https://doi.org/10.1109/EWDTS.2017.8110061 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2017.8110061 conf/ewdts/2017 db/conf/ewdts/ewdts2017.html#GulveGS17 V. S. Vineesh Nihar Hage B. Karthik Virendra Singh Achieving full functional coverage for the forwarding unit of pipelined processors. 1-4 2017 EWDTS https://doi.org/10.1109/EWDTS.2017.8110063 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2017.8110063 conf/ewdts/2017 db/conf/ewdts/ewdts2017.html#VineeshHKS17 Abhishek Rajgadia Newton Virendra Singh EEAL: Processors' Performance Enhancement Through Early Execution of Aliased Loads. 113-118 2017 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/3060403.3060445 conf/glvlsi/2017 db/conf/glvlsi/glvlsi2017.html#RajgadiaNS17 Binod Kumar 0001 Ankit Jindal Masahiro Fujita 0004 Virendra Singh Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. 191-196 2017 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/3060403.3060475 https://www.wikidata.org/entity/Q130961807 conf/glvlsi/2017 db/conf/glvlsi/glvlsi2017.html#KumarJFS17 Binod Kumar 0001 Kanad Basu Masahiro Fujita 0004 Virendra Singh RTL level trace signal selection and coverage estimation during post-silicon validation. 59-66 2017 HLDVT https://doi.org/10.1109/HLDVT.2017.8167464 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2017.8167464 conf/hldvt/2017 db/conf/hldvt/hldvt2017.html#0001BFS17 Newton Sujit Kr Mahto Suhit Pai Virendra Singh DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching. 345-352 2017 ICCD https://doi.org/10.1109/ICCD.2017.60 https://doi.ieeecomputersociety.org/10.1109/ICCD.2017.60 conf/iccd/2017 db/conf/iccd/iccd2017.html#NewtonMPS17 Binod Kumar 0001 Ankit Jindal Jaynarayan T. Tudu Brajesh Pandey Virendra Singh Revisiting random access scan for effective enhancement of post-silicon observability. 132-137 2017 IOLTS https://doi.org/10.1109/IOLTS.2017.8046208 conf/iolts/2017 db/conf/iolts/iolts2017.html#0001JTPS17 Toral Shah Anzhela Yu. Matrosova Virendra Singh Test pattern generation to detect multiple faults in ROBDD based combinational circuits. 211-212 2017 IOLTS https://doi.org/10.1109/IOLTS.2017.8046223 conf/iolts/2017 db/conf/iolts/iolts2017.html#ShahMS17 Nihar Hage Rohini Gulve Masahiro Fujita 0004 Virendra Singh Instruction-based self-test for delay faults maximizing operating temperature. 259-264 2017 IOLTS https://doi.org/10.1109/IOLTS.2017.8046231 conf/iolts/2017 db/conf/iolts/iolts2017.html#HageGFS17 Satyadev Ahlawat Darshit Vaghani Rohini Gulve Virendra Singh A low cost technique for scan chain diagnosis. 1-4 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8050440 conf/iscas/2017 db/conf/iscas/iscas2017.html#AhlawatVGS17 Ankush Srivastava Adit D. Singh Virendra Singh Kewal K. Saluja Exploiting path delay test generation to develop better TDF tests for small delay defects. 1-10 2017 ITC https://doi.org/10.1109/TEST.2017.8242072 conf/itc/2017 db/conf/itc/itc2017.html#SrivastavaSSS17 Binod Kumar 0001 Ankit Jindal Masahiro Fujita 0004 Virendra Singh Post-silicon observability enhancement with topology based trace signal selection. 1-6 2017 LATS https://doi.org/10.1109/LATW.2017.7906761 conf/latw/2017 db/conf/latw/lats2017.html#KumarJFS17 Toral Shah Anzhela Yu. Matrosova Binod Kumar 0001 Masahiro Fujita 0004 Virendra Singh Testing multiple stuck-at faults of ROBDD based combinational circuit design. 1-6 2017 LATS https://doi.org/10.1109/LATW.2017.7906753 conf/latw/2017 db/conf/latw/lats2017.html#ShahMKFS17 Ankush Srivastava Virendra Singh Adit D. Singh Kewal K. Saluja Identifying high variability speed-limiting paths under aging. 1-6 2017 LATS https://doi.org/10.1109/LATW.2017.7906757 conf/latw/2017 db/conf/latw/lats2017.html#SrivastavaSSS17 Binod Kumar 0001 Kanad Basu Ankit Jindal Masahiro Fujita 0004 Virendra Singh Improving post-silicon error detection with topological selection of trace signals. 1-6 2017 VLSI-SoC https://doi.org/10.1109/VLSI-SoC.2017.8203485 conf/vlsi/2017soc db/conf/vlsi/vlsisoc2017.html#0001BJFS17 Binod Kumar 0001 Ankit Jindal Virendra Singh Masahiro Fujita 0004 A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. 147-152 2017 VLSID https://doi.org/10.1109/VLSID.2017.66 https://doi.ieeecomputersociety.org/10.1109/VLSID.2017.66 conf/vlsid/2017 db/conf/vlsid/vlsid2017.html#KumarJSF17 Nihar Hage Rohini Gulve Masahiro Fujita 0004 Virendra Singh On Testing of Superscalar Processors in Functional Mode for Delay Faults. 397-402 2017 VLSID https://doi.org/10.1109/VLSID.2017.58 https://doi.ieeecomputersociety.org/10.1109/VLSID.2017.58 conf/vlsid/2017 db/conf/vlsid/vlsid2017.html#HageGFS17 Rudrapatna K. Shyamasundar Virendra Singh Jaideep Vaidya Information Systems Security - 13th International Conference, ICISS 2017, Mumbai, India, December 16-20, 2017, Proceedings ICISS Springer 2017 Lecture Notes in Computer Science 10717 978-3-319-72597-0 978-3-319-72598-7 https://doi.org/10.1007/978-3-319-72598-7 db/conf/iciss/iciss2017.html Brajesh Kumar Kaushik Sudeb Dasgupta Virendra Singh VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers VDAT Springer 2017 Communications in Computer and Information Science 711 978-981-10-7469-1 978-981-10-7470-7 https://doi.org/10.1007/978-981-10-7470-7 db/conf/vdat/vdat2017.html Satyadev Ahlawat Darshit Vaghani Rohini Gulve Virendra Singh Enabling LOS delay test with slow scan enable. 1-4 2016 EWDTS https://doi.org/10.1109/EWDTS.2016.7807648 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2016.7807648 conf/ewdts/2016 db/conf/ewdts/ewdts2016.html#AhlawatVGS16 Nirmal Kumar Boran Rameshwar Prasad Meghwal Kuldeep Sharma Binod Kumar 0001 Virendra Singh Performance modelling of heterogeneous ISA multicore architectures. 1-4 2016 EWDTS https://doi.org/10.1109/EWDTS.2016.7807641 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2016.7807641 conf/ewdts/2016 db/conf/ewdts/ewdts2016.html#BoranMSKS16 Rohini Gulve Virendra Singh ILP based don't care bits filling technique for reducing capture power. 1-4 2016 EWDTS https://doi.org/10.1109/EWDTS.2016.7807649 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2016.7807649 conf/ewdts/2016 db/conf/ewdts/ewdts2016.html#GulveS16 Binod Kumar 0001 Ankit Jindal Virendra Singh A trace signal selection algorithm for improved post-silicon debug. 1-4 2016 EWDTS https://doi.org/10.1109/EWDTS.2016.7807700 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2016.7807700 conf/ewdts/2016 db/conf/ewdts/ewdts2016.html#KumarJS16 Binod Kumar 0001 Boda Nehru Brajesh Pandey Virendra Singh Jaynarayan T. Tudu A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. 1-4 2016 EWDTS https://doi.org/10.1109/EWDTS.2016.7807675 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2016.7807675 conf/ewdts/2016 db/conf/ewdts/ewdts2016.html#KumarNPST16 Toral Shah Virendra Singh Anzhela Yu. Matrosova ROBDD based path delay fault testable combinational circuit synthesis. 1-4 2016 EWDTS https://doi.org/10.1109/EWDTS.2016.7807682 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2016.7807682 conf/ewdts/2016 db/conf/ewdts/ewdts2016.html#ShahSM16 Shoba Gopalakrishnan Virendra Singh REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture. 109-114 2016 IOLTS https://doi.org/10.1109/IOLTS.2016.7604681 conf/iolts/2016 db/conf/iolts/iolts2016.html#GopalakrishnanS16 Satyadev Ahlawat Jaynarayan T. Tudu Anzhela Yu. Matrosova Virendra Singh A high performance scan flip-flop design for serial and mixed mode scan test. 233-238 2016 IOLTS https://doi.org/10.1109/IOLTS.2016.7604709 conf/iolts/2016 db/conf/iolts/iolts2016.html#AhlawatTMS16 Satyadev Ahlawat Jaynarayan T. Tudu Anzhela Yu. Matrosova Virendra Singh A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. 25-30 2015 ATS https://doi.org/10.1109/ATS.2015.12 https://doi.ieeecomputersociety.org/10.1109/ATS.2015.12 conf/ats/2015 db/conf/ats/ats2015.html#AhlawatTMS15 Virendra Singh Adit D. Singh Kewal K. Saluja A Methodology for Identifying High Timing Variability Paths in Complex Designs. 115-120 2015 ATS https://doi.org/10.1109/ATS.2015.27 https://doi.ieeecomputersociety.org/10.1109/ATS.2015.27 conf/ats/2015 db/conf/ats/ats2015.html#SinghSS15 Adithyalal P. M Shankar Balachandran Virendra Singh A Soft Error Resilient Low Leakage SRAM Cell Design. 133-138 2015 ATS https://doi.org/10.1109/ATS.2015.30 https://doi.ieeecomputersociety.org/10.1109/ATS.2015.30 conf/ats/2015 db/conf/ats/ats2015.html#MBS15 Parth Lathigara Shankar Balachandran Virendra Singh Application behavior aware re-reference interval prediction for shared LLC. 172-179 2015 ICCD https://doi.org/10.1109/ICCD.2015.7357099 https://doi.ieeecomputersociety.org/10.1109/ICCD.2015.7357099 conf/iccd/2015 db/conf/iccd/iccd2015.html#LathigaraBS15 Toral Shah Anzhela Yu. Matrosova Virendra Singh PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. 1-2 2015 VDAT https://doi.org/10.1109/ISVDAT.2015.7208130 https://doi.ieeecomputersociety.org/10.1109/ISVDAT.2015.7208130 conf/vdat/2015 db/conf/vdat/vdat2015.html#ShahMS15

Dimitar Nikolov Urban Ingelsson Virendra Singh Erik Larsson Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems. 1022-1049 2014 54 Microelectron. Reliab. 5 https://doi.org/10.1016/j.microrel.2014.02.004 db/journals/mr/mr54.html#NikolovISL14

Nahit Pawar Madhu N. Belur Mani Bhushan A. P. Tiwari M. G. Kelkar M. Pramanik Virendra Singh A data-driven adaptive model-identification based large-scale sensor management system: Application to self powered neutron detectors. 1-7 2014 EAIS https://doi.org/10.1109/EAIS.2014.6867471 conf/eais/2014 db/conf/eais/eais2014.html#PawarBBTKPS14 Anzhela Yu. Matrosova Sergey Ostanin Irina Kirienko Virendra Singh Partially programmable circuit design. 1-4 2014 EWDTS https://doi.org/10.1109/EWDTS.2014.7027067 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2014.7027067 conf/ewdts/2014 db/conf/ewdts/ewdts2014.html#MatrosovaOKS14 Indira Rawat M. K. Gupta Virendra Singh Temperature aware test scheduling by modified floorplanning. 1-4 2014 EWDTS https://doi.org/10.1109/EWDTS.2014.7027087 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2014.7027087 conf/ewdts/2014 db/conf/ewdts/ewdts2014.html#RawatGS14 Lokesh Siddhu Amit Mishra 0002 Virendra Singh Operand Isolation with Reduced Overhead for Low Power Datapath Design. 483-488 2014 VLSID https://doi.org/10.1109/VLSID.2014.90 https://doi.ieeecomputersociety.org/10.1109/VLSID.2014.90 conf/vlsid/2014 db/conf/vlsid/vlsid2014.html#SiddhuMS14

Anzhela Yu. Matrosova Sergey A. Ostanin Virendra Singh Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. 1164-1177 2013 74 Autom. Remote. Control. 7 https://doi.org/10.1134/S0005117913070084 db/journals/aarc/aarc74.html#MatrosovaOS13

Indira Rawat M. K. Gupta Virendra Singh Thermal analysis and modeling of 3D integrated circuits for test scheduling. 1-5 2013 3DIC https://doi.org/10.1109/3DIC.2013.6702374 conf/3dic/2013 db/conf/3dic/3dic2013.html#RawatGS13 Anzhela Yu. Matrosova Eugeniy Mitrofanov Virendra Singh Delay testable sequential circuit designs. 1-4 2013 EWDTS https://doi.org/10.1109/EWDTS.2013.6673138 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2013.6673138 conf/ewdts/2013 db/conf/ewdts/ewdts2013.html#MatrosovaMS13 Anzhela Yu. Matrosova Ekaterina Nikolaeva Dmitry Kudin Virendra Singh PDF testability of the circuits derived by special covering ROBDDs with gates. 1-5 2013 EWDTS https://doi.org/10.1109/EWDTS.2013.6673183 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2013.6673183 conf/ewdts/2013 db/conf/ewdts/ewdts2013.html#MatrosovaNKS13 Anzhela Yu. Matrosova Sergey Ostanin Alexey Melnikov 0002 Virendra Singh Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques. 1-6 2013 EWDTS https://doi.org/10.1109/EWDTS.2013.6673184 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2013.6673184 conf/ewdts/2013 db/conf/ewdts/ewdts2013.html#MatrosovaOMS13 Indira Rawat M. K. Gupta Virendra Singh Scheduling tests for 3D SoCs with temperature constraints. 1-4 2013 EWDTS https://doi.org/10.1109/EWDTS.2013.6673214 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2013.6673214 conf/ewdts/2013 db/conf/ewdts/ewdts2013.html#RawatGS13 Jaynarayan T. Tudu Deepak Malani Virendra Singh Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP. 345-352 2013 VDAT https://doi.org/10.1007/978-3-642-42024-5_41 conf/vdat/2013 db/conf/vdat/vdat2013.html#TuduMS13 Prabhat Mishra 0001 Masahiro Fujita 0004 Virendra Singh Nagesh Tamarapalli Sharad Kumar Rajesh Mittal Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. 2013 VLSI Design https://doi.org/10.1109/VLSID.2013.145 https://doi.ieeecomputersociety.org/10.1109/VLSID.2013.145 conf/vlsid/2013 db/conf/vlsid/vlsid2013.html#MishraFSTKM13 Manoj Singh Gaur Mark Zwolinski Vijay Laxmi Dharmendar Boolchandani Virendra Singh Adit D. Singh VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers Springer 2013 978-3-642-42023-8 978-3-642-42024-5 Communications in Computer and Information Science 382 https://doi.org/10.1007/978-3-642-42024-5 VDAT db/conf/vdat/vdat2013.html

Suraj Sindia Vishwani D. Agrawal Virendra Singh Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. 541-549 2012 28 J. Electron. Test. 4 https://doi.org/10.1007/s10836-012-5305-4 db/journals/et/et28.html#SindiaAS12

Suraj Sindia Vishwani D. Agrawal Virendra Singh Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. 757-771 2012 28 J. Electron. Test. 5 https://doi.org/10.1007/s10836-012-5326-z db/journals/et/et28.html#SindiaAS12a

Mohammed Shayan Virendra Singh Adit D. Singh Masahiro Fujita 0004 SEU tolerant robust memory cell design. 13-18 2012 IOLTS https://doi.org/10.1109/IOLTS.2012.6313834 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2012.6313834 conf/iolts/2012 db/conf/iolts/iolts2012.html#ShayanSSF12 Suraj Sindia Fa Foster Dai Vishwani D. Agrawal Virendra Singh Impact of process variations on computers used for image processing. 1444-1447 2012 ISCAS https://doi.org/10.1109/ISCAS.2012.6271517 conf/iscas/2012 db/conf/iscas/iscas2012.html#SindiaDAS12 Pawan Kumar Virendra Singh Efficient regular expression pattern matching for network intrusion detection systems using modified word-based automata. 103-110 2012 SIN https://doi.org/10.1145/2388576.2388590 conf/sin/2012 db/conf/sin/sin2012.html#KumarS12 Jaynarayan T. Tudu Deepak Malani Virendra Singh ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. 172-179 2012 VDAT https://doi.org/10.1007/978-3-642-31494-0_20 conf/vdat/2012 db/conf/vdat/vdat2012.html#TuduMS12 Mohammed Shayan Virendra Singh Adit D. Singh Masahiro Fujita 0004 SEU Tolerant Robust Latch Design. 223-232 2012 VDAT https://doi.org/10.1007/978-3-642-31494-0_26 conf/vdat/2012 db/conf/vdat/vdat2012.html#ShayanSSF12 V. Prasanth 0001 Virendra Singh Rubin A. Parekhji Derating based hardware optimizations in soft error tolerant designs. 282-287 2012 VTS https://doi.org/10.1109/VTS.2012.6231067 conf/vts/2012 db/conf/vts/vts2012.html#PrasanthSP12 Manoj Singh Gaur Atilla Elçi Oleg B. Makarevich Mehmet A. Orgun Virendra Singh 5th International Conference of Security of Information and Networks, SIN '12, Jaipur, India, October 22 - 26, 2012 ACM SIN 2012 978-1-4503-1668-2 http://dl.acm.org/citation.cfm?id=2388576 db/conf/sin/sin2012.html Mohammed Abdul Razzaq Virendra Singh Adit D. Singh SSTKR: Secure and Testable Scan Design through Test Key Randomization. 60-65 2011 Asian Test Symposium https://doi.org/10.1109/ATS.2011.85 https://doi.ieeecomputersociety.org/10.1109/ATS.2011.85 conf/ats/2011 db/conf/ats/ats2011.html#RazzaqSS11 Suraj Sindia Vishwani D. Agrawal Virendra Singh Test and Diagnosis of Analog Circuits Using Moment Generating Functions. 371-376 2011 Asian Test Symposium https://doi.org/10.1109/ATS.2011.86 https://doi.ieeecomputersociety.org/10.1109/ATS.2011.86 conf/ats/2011 db/conf/ats/ats2011.html#SindiaAS11 Naveen Choudhary Manoj Singh Gaur Vijay Laxmi Virendra Singh GA Based Congestion Aware Topology Generation for Application Specific NoC. 93-98 2011 DELTA https://doi.org/10.1109/DELTA.2011.26 https://doi.ieeecomputersociety.org/10.1109/DELTA.2011.26 conf/delta/2011 db/conf/delta/delta2011.html#ChoudharyGLS11 Dimitar Nikolov Urban Ingelsson Virendra Singh Erik Larsson Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization. 59-64 2011 DSN Workshops https://doi.org/10.1109/DSNW.2011.5958836 https://doi.ieeecomputersociety.org/10.1109/DSNW.2011.5958836 conf/dsn/2011w db/conf/dsn/dsnw2011.html#NikolovISL11 Anzhela Yu. Matrosova Alexey Melnikov 0002 Ruslan Mukhamedov Virendra Singh Selection of the state variables for partial enhanced scan techniques. 285-290 2011 EWDTS https://doi.org/10.1109/EWDTS.2011.6116413 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2011.6116413 conf/ewdts/2011 db/conf/ewdts/ewdts2011.html#MatrosovaMMS11 Harsh Gidra Israrul Haque Nitin P. Kumar M. Sargurunathan Manoj Singh Gaur Vijay Laxmi Mark Zwolinski Virendra Singh Parallelizing TUNAMI-N1 Using GPGPU. 845-850 2011 HPCC https://doi.org/10.1109/HPCC.2011.120 https://doi.ieeecomputersociety.org/10.1109/HPCC.2011.120 https://www.wikidata.org/entity/Q59245057 conf/hpcc/2011 db/conf/hpcc/hpcc2011.html#GidraHKSGLZS11 Pramod Subramanyan Virendra Singh Kewal K. Saluja Erik Larsson Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. 419-426 2011 ICCD https://doi.org/10.1109/ICCD.2011.6081432 https://doi.ieeecomputersociety.org/10.1109/ICCD.2011.6081432 conf/iccd/2011 db/conf/iccd/iccd2011.html#SubramanyanSSL11 V. Prasanth 0001 Virendra Singh Rubin A. Parekhji Reduced overhead soft error mitigation using error control coding techniques. 163-168 2011 IOLTS https://doi.org/10.1109/IOLTS.2011.5993831 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2011.5993831 conf/iolts/2011 db/conf/iolts/iolts2011.html#PrasanthSP11 Sudipta Sarkar Anubhav Adak Virendra Singh Kewal K. Saluja Masahiro Fujita 0004 SEU tolerant SRAM cell. 597-602 2011 ISQED https://doi.org/10.1109/ISQED.2011.5770789 conf/isqed/2011 db/conf/isqed/isqed2011.html#SarkarASSF11 Suraj Sindia Vishwani D. Agrawal Virendra Singh Testing linear and non-linear analog circuits using moment generating functions. 1-6 2011 LATW https://doi.org/10.1109/LATW.2011.5985915 conf/latw/2011 db/conf/latw/latw2011.html#SindiaAS11 Virendra Singh Masahiro Fujita 0004 Tutorial: "Post silicon debug of SOC designs". 18 2011 SoCC https://doi.org/10.1109/SOCC.2011.6085147 conf/socc/2011 db/conf/socc/socc2011.html#SinghF11 Manas Kumar Puthal Virendra Singh Manoj Singh Gaur Vijay Laxmi C-Routing: An adaptive hierarchical NoC routing methodology. 392-397 2011 VLSI-SoC https://doi.org/10.1109/VLSISoC.2011.6081616 conf/vlsi/2011soc db/conf/vlsi/vlsisoc2011.html#PuthalSGL11 Suraj Sindia Vishwani D. Agrawal Virendra Singh Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. 64-69 2011 VTS https://doi.org/10.1109/VTS.2011.5783756 conf/vts/2011 db/conf/vts/vts2011.html#SindiaAS11 Amit Mishra 0002 Nidhi Sinha Satdev Virendra Singh Sreejit Chakravarty Adit D. Singh Modified Scan Flip-Flop for Low Power Testing. 367-370 2010 Asian Test Symposium https://doi.org/10.1109/ATS.2010.69 https://doi.ieeecomputersociety.org/10.1109/ATS.2010.69 conf/ats/2010 db/conf/ats/ats2010.html#MishraSSSCS10 Pramod Subramanyan Virendra Singh Kewal K. Saluja Erik Larsson Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. 1572-1577 2010 DATE https://doi.org/10.1109/DATE.2010.5457061 http://dl.acm.org/citation.cfm?id=1871304 conf/date/2010 db/conf/date/date2010.html#SubramanyanSSL10 Dimitar Nikolov Urban Ingelsson Virendra Singh Erik Larsson Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing. 281-285 2010 DELTA https://doi.org/10.1109/DELTA.2010.25 https://doi.ieeecomputersociety.org/10.1109/DELTA.2010.25 conf/delta/2010 db/conf/delta/delta2010.html#NikolovISL10 Pramod Subramanyan Virendra Singh Kewal K. Saluja Erik Larsson Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. 121-130 2010 DSN https://doi.org/10.1109/DSN.2010.5544918 https://doi.ieeecomputersociety.org/10.1109/DSN.2010.5544918 conf/dsn/2010 db/conf/dsn/dsn2010.html#SubramanyanSSL10 Raghavendra Adiga Gandhi Arpit Virendra Singh Kewal K. Saluja Adit D. Singh Modified T-Flip-Flop based scan cell for RAS. 113-118 2010 ETS https://doi.org/10.1109/ETSYM.2010.5512773 conf/ets/2010 db/conf/ets/ets2010.html#AdigaASSS10 Jaynarayan T. Tudu Erik Larsson Virendra Singh Hideo Fujiwara Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. 259 2010 ETS https://doi.org/10.1109/ETSYM.2010.5512732 conf/ets/2010 db/conf/ets/ets2010.html#TuduLSF10 Anzhela Yu. Matrosova Valeriy B. Lipsky Alexey Melnikov 0002 Virendra Singh Path delay faults and ENF. 164-167 2010 EWDTS https://doi.org/10.1109/EWDTS.2010.5742130 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2010.5742130 conf/ewdts/2010 db/conf/ewdts/ewdts2010.html#MatrosovaLMS10 Aditi Kajala Gayaprasad Sinsinwar Rahul Raj Choudhary Jaynarayan T. Tudu Virendra Singh On selection of state variables for delay test of identical functional units. 200-203 2010 EWDTS https://doi.org/10.1109/EWDTS.2010.5742119 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2010.5742119 conf/ewdts/2010 db/conf/ewdts/ewdts2010.html#KajalaSCTS10 Viney Kumar Rahul Raj Choudhary Virendra Singh FREP: A soft error resilient pipelined RISC architecture. 330-333 2010 EWDTS https://doi.org/10.1109/EWDTS.2010.5742103 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2010.5742103 conf/ewdts/2010 db/conf/ewdts/ewdts2010.html#KumarCS10 N. S. Vinay Indira Rawat Erik Larsson Manoj Singh Gaur Virendra Singh Thermal aware test scheduling for stacked multi-chip-modules. 343-349 2010 EWDTS https://doi.org/10.1109/EWDTS.2010.5742053 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2010.5742053 conf/ewdts/2010 db/conf/ewdts/ewdts2010.html#VinayRLGS10 K. R. Vinutha Virendra Singh Anzhela Yu. Matrosova Manoj Singh Gaur Fault grading using Instruction-Execution graph. 350-357 2010 EWDTS https://doi.org/10.1109/EWDTS.2010.5742054 https://doi.ieeecomputersociety.org/10.1109/EWDTS.2010.5742054 conf/ewdts/2010 db/conf/ewdts/ewdts2010.html#VinuthaSMG10 Sudipta Sarkar Anubhav Adak Virendra Singh Kewal K. Saluja Masahiro Fujita 0004 SEU tolerant SRAM for FPGA applications. 491-494 2010 FPT https://doi.org/10.1109/FPT.2010.5681465 conf/fpt/2010 db/conf/fpt/fpt2010.html#SarkarASSF10 Jaynarayan T. Tudu Erik Larsson Virendra Singh Hideo Fujiwara Graph theoretic approach for scan cell reordering to minimize peak shift power. 73-78 2010 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1785481.1785499 conf/glvlsi/2010 db/conf/glvlsi/glvlsi2010.html#TuduLSF10 Pramod Subramanyan Virendra Singh Kewal K. Saluja Erik Larsson Energy-efficient redundant execution for chip multiprocessors. 143-146 2010 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1785481.1785516 conf/glvlsi/2010 db/conf/glvlsi/glvlsi2010.html#SubramanyanSSL10 V. Prasanth 0001 Virendra Singh Rubin A. Parekhji Robust detection of soft errors using delayed capture methodology. 277-282 2010 IOLTS https://doi.org/10.1109/IOLTS.2010.5560188 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560188 conf/iolts/2010 db/conf/iolts/iolts2010.html#PrasanthSP10 A. Abhishek Amanulla Khan Virendra Singh Kewal K. Saluja Adit D. Singh Test application time minimization for RAS using basis optimization of column decoder. 2614-2617 2010 ISCAS https://doi.org/10.1109/ISCAS.2010.5537094 conf/iscas/2010 db/conf/iscas/iscas2010.html#AbhishekKSSS10 Naveen Choudhary Manoj Singh Gaur Vijay Laxmi Virendra Singh Genetic algorithm based topology generation for application specific Network-on-Chip. 3156-3159 2010 ISCAS https://doi.org/10.1109/ISCAS.2010.5537952 conf/iscas/2010 db/conf/iscas/iscas2010.html#ChoudharyGLS10 Suraj Sindia Virendra Singh Vishwani D. Agrawal Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. 288-293 2010 VLSI Design https://doi.org/10.1109/VLSI.Design.2010.81 https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.81 conf/vlsid/2010 db/conf/vlsid/vlsid2010.html#SindiaSA10 Raghavendra Adiga Gandhi Arpit Virendra Singh Kewal K. Saluja Hideo Fujiwara Adit D. Singh On Minimization of Test Application Time for RAS. 393-398 2010 VLSI Design https://doi.org/10.1109/VLSI.Design.2010.61 https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.61 conf/vlsid/2010 db/conf/vlsid/vlsid2010.html#AdigaASSFS10 Suraj Sindia Virendra Singh Vishwani D. Agrawal Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. 63-68 2009 Asian Test Symposium https://doi.org/10.1109/ATS.2009.45 https://doi.ieeecomputersociety.org/10.1109/ATS.2009.45 conf/ats/2009 db/conf/ats/ats2009.html#SindiaSA09 K. G. Deepak Robinson Reyna Virendra Singh Adit D. Singh Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. 237-240 2009 Asian Test Symposium https://doi.org/10.1109/ATS.2009.78 https://doi.ieeecomputersociety.org/10.1109/ATS.2009.78 conf/ats/2009 db/conf/ats/ats2009.html#DeepakRSS09 Mikael Väyrynen Virendra Singh Erik Larsson Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. 484-489 2009 DATE https://doi.org/10.1109/DATE.2009.5090713 http://dl.acm.org/citation.cfm?id=1874740 conf/date/2009 db/conf/date/date2009.html#VayrynenSL09 Jaynarayan T. Tudu Erik Larsson Virendra Singh Vishwani D. Agrawal On Minimization of Peak Power for Scan Circuit during Test. 25-30 2009 ETS https://doi.org/10.1109/ETS.2009.36 https://doi.ieeecomputersociety.org/10.1109/ETS.2009.36 conf/ets/2009 db/conf/ets/ets2009.html#TuduLSA09 Suraj Sindia Virendra Singh Vishwani D. Agrawal Polynomial coefficient based DC testing of non-linear analog circuits. 69-74 2009 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1531542.1531562 conf/glvlsi/2009 db/conf/glvlsi/glvlsi2009.html#SindiaSA09 Reshma C. Jumani Niraj Bharatkumar Jain Virendra Singh Kewal K. Saluja DX-compactor: distributed X-compaction for SoCs. 505-510 2009 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1531542.1531657 conf/glvlsi/2009 db/conf/glvlsi/glvlsi2009.html#JumaniJSS09

Virendra Singh Michiko Inoue Kewal K. Saluja Hideo Fujiwara Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. 1203-1215 2006 14 IEEE Trans. Very Large Scale Integr. Syst. 11 https://doi.org/10.1109/TVLSI.2006.886412 db/journals/tvlsi/tvlsi14.html#SinghISF06

Virendra Singh Michiko Inoue Kewal K. Saluja Hideo Fujiwara Delay Fault Testing of Processor Cores in Functional Mode. 610-618 http://search.ieice.org/bin/summary.php?id=e88-d_3_610&category=D&year=2005&lang=E&abst= 2005 88-D IEICE Trans. Inf. Syst. 3 db/journals/ieicet/ieicet88d.html#SinghISF05

Virendra Singh Michiko Inoue Kewal K. Saluja Hideo Fujiwara Testing Superscalar Processors in Functional Mode. 747-750 2005 conf/fpl/2005 FPL db/conf/fpl/fpl2005.html#SinghISF05 https://doi.org/10.1109/FPL.2005.1515837 https://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515837 Virendra Singh Michiko Inoue Kewal K. Saluja Hideo Fujiwara Instruction-based delay fault self-testing of pipelined processor cores. 5686-5689 2005 conf/iscas/2005 ISCAS (6) https://doi.org/10.1109/ISCAS.2005.1465928 db/conf/iscas/iscas2005-6.html#SinghISF05 Virendra Singh Michiko Inoue Kewal K. Saluja Hideo Fujiwara Instruction-Based Delay Fault Self-Testing of Processor Cores. 933- 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1261051 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261051 db/conf/vlsid/vlsid2004.html#SinghIKF04 Virendra Singh Michiko Inoue Kewal K. Saluja Hideo Fujiwara Software-Based Delay Fault Testing of Processor Cores. 68-71 2003 conf/ats/2003 Asian Test Symposium https://doi.org/10.1109/ATS.2003.1250785 https://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250785 db/conf/ats/ats2003.html#SinghISF03 A. Abhishek Adnan M. Abu-Mahfouz Anubhav Adak Jay Adhaduk Raghavendra Adiga Vishwani D. Agrawal Kailash Ahirwar Satyadev Ahlawat Wadee Alhalabi Insha Amin Abhinish Anand Gandhi Arpit Varsha Arya Sarath Babu 0003 Rohit Badjatya Shankar Balachandran N. B. Balamurugan Jaydev Bapat Kanad Basu Gourav Bathla Naveen Bazard Madhu N. Belur Harsh Bhargav Harsh Bhargava Lava Bhargava Shrasti Bhargava Pushpak Bhattacharyya Atul Kumar Bhosale Mani Bhushan Tarun Bisht Supratim Biswas Dharmendar Boolchandani Nirmal Kumar Boran Riccardo Cantoro Trevor E. Carlson Sreejit Chakravarty Chandramani Chaudhary Naveen Choudhary Pooja Choudhary Rahul Raj Choudhary Raj Kumar Choudhary Foster F. DaiFa Foster Dai Pinaki Das Sudeb Dasgupta K. G. Deepak Prakhar Diwan Atilla Elçi Shariq Faraz Parvez Faruki Masahiro Fujita 0004 Hideo Fujiwara Antara Ganguly Udayan Ganguly Saurabh Gangurde Francesco Garau Manoj Singh Gaur Yogesh Gholap Prokash Ghosh Harsh Gidra Uddhav Narayan Gilda Anshu Goel Shoba Gopalakrishnan Sandeep Goyal Rohini Gulve Aditi Gupta Brij B. Gupta Harsh Gupta M. K. Gupta Maanak Gupta Shalabh Gupta Sukanya Gupta Mahendra Kumar Gurve Gholamreza Haffari Nihar Hage Israrul Haque Saumya Hegde Makoto Ikeda Urban Ingelsson Michiko Inoue Govind Rajhans Jadhav Niraj Bharatkumar Jain Akshay Jaiswal Srivatsava Jandhyala Chandan Kumar Jha 0001 Ankit Jindal Nitish Jindal Devesh C. JinwalaDevesh Jinwala Ron Joseph Pranil Joshi Reshma C. Jumani Raghunandana K. K Aditi Kajala Kushal Kamal B. Karthik Brajesh Kumar Kaushik Rushikesh Kawale M. G. Kelkar Amanulla Khan Irina Kirienko Keerthisagar Kokkiligadda Gowthami Konganapalle Munawira Kotyad Dmitry Kudin Anuj Kumar Avinash Kumar Bhavika Ranjeet Kumar Binod Kumar 0001 Gaurav Kumar 0001 Nitin P. Kumar Pawan Kumar Rahul Kumar Sharad Kumar Viney Kumar Sohan Lal Erik Larsson Parth Lathigara Vijay Laxmi Ashwin Sanjay Lele Valerii B. LipskyValeriy B. Lipsky Adithyalal P. M Sujit Kr Mahto Oleg B. Makarevich Deepak Malani Meena Malik Riccardo Masante Anzhela Yu. Matrosova Rameshwar Prasad Meghwal Alexey Melnikov 0002 Amit Mishra 0002 Deepak Mishra 0001 Prabhat Mishra 0001 Eugeniy Mitrofanov Rajesh Mittal Ruslan Mukhamedov Rajeev Muralidhar Harideep Nair Sukumar Nandi Boda Nehru NewtonNewton Singh Ekaterina Nikolaeva Dimitar Nikolov Anant NoriAnant V. Nori Kelly Ockunzzi Adeiza OnumanyiAdeiza James Onumanyi Mehmet A. Orgun Sergey OstaninSergey A. Ostanin Suhit Pai Brajesh Pandey Neeraj Panwar Rubin A. Parekhji Nikhil Kumar Parida Janak Patel Janeel Patel Nahit Pawar Prasanth Viswanathan PillaiV. Prasanth 0001 M. Pramanik Yamuna Prasad Manas Kumar Puthal Yogesh Prasad K. R S. Rajaram 0001 Abhishek Rajgadia D. Gracia Nirmala Rani Shubhankit Rathore Yashvardhan Rathore Rishab Ravi Indira Rawat Rishabh Rawat Mohammed Abdul Razzaq Matteo Sonza Reorda Robinson Reyna Anjum Riaz Vineesh V. S.V. S. Vineesh Ravikant Saini Kewal K. Saluja Jitendra Kumar Samriya N. Sangeeth Tikaram Sanyashi Durgesh Sardan M. Sargurunathan Arindam Sarkar Sudipta Sarkar Sandro Sartoni Vedant Satav Satdev Anirban Sengupta Toral Shah Ganesh Sai Shanmukhi Kapil Sharma Kuldeep Sharma Neelam Sharma Rohit Sharma Mohammed Shayan Jaidev Shenoy Rushikesh Shinde Sonali Shukla R. K. ShyamasundarRudrapatna K. Shyamasundar Lokesh Siddhu Suraj Sindia Adit D. Singh Mahendra Pratap Singh Nidhi Sinha Gayaprasad Sinsinwar Mandru Suma Sri Ankush Srivastava Pramod Subramanyan Sreenivas Subramoney Ashok Kumar Suhag Nagesh Tamarapalli Mitul Tandon Swapniel Thakur Winnie Thomas Tejeshwar Bhagatsing Thorawade Akhilanand Pati TiwariA. P. Tiwari Suryakant Toraskar Jaynarayan T. Tudu Vinod G. U Meet Udeshi Darshit Vaghani Jaideep Vaidya Veerendrababu Vakkapatla B. K. S. V. L. Varaprasad Mikael Väyrynen Anishetti Venkatesh Varun Venkitaraman Samiksha Verma N. S. Vinay G. U. Vinod K. R. Vinutha Santosh Kumar Vishvakarma Chakka Srikanth Yadav Prajakta Yeola Mark Zwolinski