Deep Learning Inference with Dynamic Graphs on Heterogeneous Platforms.

Evangelos Vassalos

Vasileios K. Pothos Evangelos Vassalos Ilias Theodorakopoulos Nikolaos Fragoulis Deep Learning Inference with Dynamic Graphs on Heterogeneous Platforms. 158-176 2021 49 Int. J. Parallel Program. 2 https://doi.org/10.1007/s10766-020-00654-2 db/journals/ijpp/ijpp49.html#PothosVTF21

Nikolaos Fragoulis Ilias Theodorakopoulos Vasileios K. Pothos Evangelos Vassalos Dynamic Pruning of CNN networks. 1-5 2019 IISA https://doi.org/10.1109/IISA.2019.8900711 conf/iisa/2019 db/conf/iisa/iisa2019.html#NikolaosTPV19 Evangelos Vassalos Dimitris Bakalis Haridimos T. Vergos Reverse converters for RNSs with diminished-one encoded channels. 1798-1805 2013 EUROCON https://doi.org/10.1109/EUROCON.2013.6625221 conf/eurocon/2013 db/conf/eurocon/eurocon2013.html#VassalosBV13 Evangelos Vassalos Dimitris Bakalis Modulo 2n-2 arithmetic units. 1806-1813 2013 EUROCON https://doi.org/10.1109/EUROCON.2013.6625222 conf/eurocon/2013 db/conf/eurocon/eurocon2013.html#VassalosB13 Evangelos Vassalos Dimitris Bakalis On the design of modulo 2n-1 cubing units. 251-256 2013 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/2483028.2483104 conf/glvlsi/2013 db/conf/glvlsi/glvlsi2013.html#VassalosB13 Evangelos Vassalos Dimitris Bakalis Haridimos T. Vergos RNS assisted image filtering and edge detection. 1-6 2013 DSP https://doi.org/10.1109/ICDSP.2013.6622821 conf/icdsp/2013 db/conf/icdsp/icdsp2013.html#VassalosBV13

Evangelos Vassalos Dimitris Bakalis CSD-RNS-based Single Constant Multipliers. 255-268 2012 67 J. Signal Process. Syst. 3 https://doi.org/10.1007/s11265-010-0552-z db/journals/vlsisp/vlsisp67.html#VassalosB12

Evangelos Vassalos Dimitris Bakalis Haridimos T. Vergos SUT-RNS Residue-to-Binary Converters Design. 65-72 2012 DSD https://doi.org/10.1109/DSD.2012.121 https://doi.ieeecomputersociety.org/10.1109/DSD.2012.121 conf/dsd/2012 db/conf/dsd/dsd2012.html#VassalosBV12

Evangelos Vassalos Dimitris Bakalis Haridimos T. Vergos On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors. 1445-1461 2011 30 Circuits Syst. Signal Process. 6 https://doi.org/10.1007/s00034-011-9326-5 db/journals/cssp/cssp30.html#VassalosBV11

Evangelos Vassalos Dimitris Bakalis Haridimos T. Vergos Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion. 468-475 2011 DSD https://doi.org/10.1109/DSD.2011.66 https://doi.ieeecomputersociety.org/10.1109/DSD.2011.66 conf/dsd/2011 db/conf/dsd/dsd2011.html#VassalosBV11 Evangelos Vassalos Dimitris Bakalis Haridimos T. Vergos On the use of double-LSB and signed-LSB encodings for RNS. 1-6 2011 DSP https://doi.org/10.1109/ICDSP.2011.6004929 conf/icdsp/2011 db/conf/icdsp/icdsp2011.html#VassalosBV11 Evangelos Vassalos Dimitris Bakalis Haridimos T. Vergos SUT-RNS Forward and Reverse Converters. 11-16 2010 ISVLSI https://doi.org/10.1109/ISVLSI.2010.23 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2010.23 conf/isvlsi/2010 db/conf/isvlsi/isvlsi2010.html#VassalosBV10 Evangelos Vassalos Dimitris Bakalis Haridimos T. Vergos SUT-RNS Forward and Reverse Converters. 231-244 2010 ISVLSI (Selected papers) https://doi.org/10.1007/978-94-007-1488-5_14 conf/isvlsi/2010s db/conf/isvlsi/isvlsi2010s.html#VassalosBV10a Evangelos Vassalos Dimitris Bakalis Combined SD-RNS Constant Multiplication. 172-179 2009 DSD https://doi.org/10.1109/DSD.2009.175 https://doi.ieeecomputersociety.org/10.1109/DSD.2009.175 conf/dsd/2009 db/conf/dsd/dsd2009.html#VassalosB09 Evangelos Vassalos Dimitris Bakalis Haridimos T. Vergos Novel modulo 2n+1 subtractors. 1-5 2009 DPS https://doi.org/10.1109/ICDSP.2009.5201052 conf/icdsp/2009 db/conf/icdsp/icdsp2009.html#VassalosBV09 Dimitris Bakalis Nikos FragoulisNikolaos Fragoulis Vasileios K. Pothos Ilias Theodorakopoulos Haridimos T. Vergos