Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.

Yoshiki Saito Tomoaki Shirai Takuro Nakamura Takashi Nishimura Yohei Hasegawa Satoshi Tsutsumi Toshihiro Kashima Mitsutaka Nakata Seidai Takeda Kimiyoshi Usami Hideharu Amano Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. 329-332 2008 FPT https://doi.org/10.1109/FPT.2008.4762410 conf/fpt/2008 db/conf/fpt/fpt2008.html#SaitoSNNHTKNTUA08