Binod Kumar 0001 Kanad Basu Masahiro Fujita 0004 Virendra Singh Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. 248-261 2020 39 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/TCAD.2018.2883899 https://www.wikidata.org/entity/Q128869022 db/journals/tcad/tcad39.html#KumarBFS20