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dpgeorgedpgeorge
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stm32/mboot: Allow a board to fully configure system clocks.
If a board wants to customise the clocks it can define the following: MBOOT_CLK_PLLM MBOOT_CLK_PLLN MBOOT_CLK_PLLP MBOOT_CLK_PLLQ MBOOT_CLK_PLLR (only needed on STM32H7) MBOOT_FLASH_LATENCY MBOOT_CLK_AHB_DIV MBOOT_CLK_APB1_DIV MBOOT_CLK_APB2_DIV MBOOT_CLK_APB3_DIV (only needed on STM32H7) MBOOT_CLK_APB4_DIV (only needed on STM32H7) Signed-off-by: Damien George <[email protected]>
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‎ports/stm32/mboot/main.c

Lines changed: 53 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -60,31 +60,38 @@
6060
// Most values are defined in irq.h.
6161
#define IRQ_PRI_I2C (NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 1, 0))
6262

63-
// Configure PLL to give the desired CPU freq
64-
#undef MICROPY_HW_FLASH_LATENCY
65-
#if defined(STM32F4) || defined(STM32F7)
66-
#if MBOOT_ENABLE_PACKING
67-
// With encryption/signing/compression, a faster CPU makes processing much faster.
63+
#if defined(MBOOT_CLK_PLLM)
64+
// The board specified the PLL values, flash latency and bus dividers
65+
#define CORE_PLL_FREQ (1000000 * MBOOT_CLK_PLLN / MBOOT_CLK_PLLP)
66+
#else
67+
// The board did not specify the clock values, so configure defaults
68+
#if defined(STM32F4) || defined(STM32F7)
69+
#if MBOOT_ENABLE_PACKING
70+
// With encryption/signing/compression, a faster CPU makes processing much faster.
71+
#define CORE_PLL_FREQ (96000000)
72+
#define MBOOT_FLASH_LATENCY FLASH_LATENCY_3
73+
#else
74+
#define CORE_PLL_FREQ (48000000)
75+
#define MBOOT_FLASH_LATENCY FLASH_LATENCY_1
76+
#endif
77+
#define MBOOT_CLK_AHB_DIV (RCC_SYSCLK_DIV1)
78+
#define MBOOT_CLK_APB1_DIV (RCC_HCLK_DIV4)
79+
#define MBOOT_CLK_APB2_DIV (RCC_HCLK_DIV2)
80+
#elif defined(STM32H7)
6881
#define CORE_PLL_FREQ (96000000)
69-
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_3
70-
#else
71-
#define CORE_PLL_FREQ (48000000)
72-
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_1
82+
#define MBOOT_FLASH_LATENCY FLASH_LATENCY_2
83+
#define MBOOT_CLK_AHB_DIV (RCC_HCLK_DIV2)
84+
#define MBOOT_CLK_APB1_DIV (RCC_APB1_DIV2)
85+
#define MBOOT_CLK_APB2_DIV (RCC_APB2_DIV2)
86+
#define MBOOT_CLK_APB3_DIV (RCC_APB3_DIV2)
87+
#define MBOOT_CLK_APB4_DIV (RCC_APB4_DIV2)
7388
#endif
74-
#elif defined(STM32H7)
75-
#define CORE_PLL_FREQ (96000000)
76-
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_2
89+
#define MBOOT_CLK_PLLM (MICROPY_HW_CLK_VALUE / 1000000)
90+
#define MBOOT_CLK_PLLN (192)
91+
#define MBOOT_CLK_PLLP (MBOOT_CLK_PLLN / (CORE_PLL_FREQ / 1000000))
92+
#define MBOOT_CLK_PLLQ (4)
93+
#define MBOOT_CLK_PLLR (2)
7794
#endif
78-
#undef MICROPY_HW_CLK_PLLM
79-
#undef MICROPY_HW_CLK_PLLN
80-
#undef MICROPY_HW_CLK_PLLP
81-
#undef MICROPY_HW_CLK_PLLQ
82-
#undef MICROPY_HW_CLK_PLLR
83-
#define MICROPY_HW_CLK_PLLM (MICROPY_HW_CLK_VALUE / 1000000)
84-
#define MICROPY_HW_CLK_PLLN (192)
85-
#define MICROPY_HW_CLK_PLLP (MICROPY_HW_CLK_PLLN / (CORE_PLL_FREQ / 1000000))
86-
#define MICROPY_HW_CLK_PLLQ (4)
87-
#define MICROPY_HW_CLK_PLLR (2)
8895

8996
// Work out which USB device to use for the USB DFU interface
9097
#if !defined(MICROPY_HW_USB_MAIN_DEV)
@@ -203,10 +210,10 @@ void SystemClock_Config(void) {
203210
#else
204211
1 << RCC_PLLCFGR_PLLSRC_Pos // HSE selected as PLL source
205212
#endif
206-
| MICROPY_HW_CLK_PLLM << RCC_PLLCFGR_PLLM_Pos
207-
| MICROPY_HW_CLK_PLLN << RCC_PLLCFGR_PLLN_Pos
208-
| ((MICROPY_HW_CLK_PLLP >> 1) - 1) << RCC_PLLCFGR_PLLP_Pos
209-
| MICROPY_HW_CLK_PLLQ << RCC_PLLCFGR_PLLQ_Pos
213+
| MBOOT_CLK_PLLM << RCC_PLLCFGR_PLLM_Pos
214+
| MBOOT_CLK_PLLN << RCC_PLLCFGR_PLLN_Pos
215+
| ((MBOOT_CLK_PLLP >> 1) - 1) << RCC_PLLCFGR_PLLP_Pos
216+
| MBOOT_CLK_PLLQ << RCC_PLLCFGR_PLLQ_Pos
210217
#ifdef RCC_PLLCFGR_PLLR
211218
| 2 << RCC_PLLCFGR_PLLR_Pos // default PLLR value of 2
212219
#endif
@@ -218,26 +225,26 @@ void SystemClock_Config(void) {
218225
}
219226

220227
// Increase latency before changing clock
221-
if (MICROPY_HW_FLASH_LATENCY > (FLASH->ACR & FLASH_ACR_LATENCY)) {
222-
__HAL_FLASH_SET_LATENCY(MICROPY_HW_FLASH_LATENCY);
228+
if (MBOOT_FLASH_LATENCY > (FLASH->ACR & FLASH_ACR_LATENCY)) {
229+
__HAL_FLASH_SET_LATENCY(MBOOT_FLASH_LATENCY);
223230
}
224231

225232
// Configure AHB divider
226-
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
233+
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, MBOOT_CLK_AHB_DIV);
227234

228235
// Configure SYSCLK source from PLL
229236
__HAL_RCC_SYSCLK_CONFIG(RCC_SYSCLKSOURCE_PLLCLK);
230237
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) {
231238
}
232239

233240
// Decrease latency after changing clock
234-
if (MICROPY_HW_FLASH_LATENCY < (FLASH->ACR & FLASH_ACR_LATENCY)) {
235-
__HAL_FLASH_SET_LATENCY(MICROPY_HW_FLASH_LATENCY);
241+
if (MBOOT_FLASH_LATENCY < (FLASH->ACR & FLASH_ACR_LATENCY)) {
242+
__HAL_FLASH_SET_LATENCY(MBOOT_FLASH_LATENCY);
236243
}
237244

238245
// Set APB clock dividers
239-
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV4);
240-
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV2 << 3);
246+
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, MBOOT_CLK_APB1_DIV);
247+
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, MBOOT_CLK_APB2_DIV << 3);
241248

242249
// Update clock value and reconfigure systick now that the frequency changed
243250
SystemCoreClock = CORE_PLL_FREQ;
@@ -281,14 +288,14 @@ void SystemClock_Config(void) {
281288
RCC->PLLCFGR = 0;
282289

283290
// Configure PLL1 for use by SYSCLK
284-
RCC->PLLCKSELR |= MICROPY_HW_CLK_PLLM << RCC_PLLCKSELR_DIVM1_Pos;
291+
RCC->PLLCKSELR |= MBOOT_CLK_PLLM << RCC_PLLCKSELR_DIVM1_Pos;
285292
RCC->PLLCFGR |= RCC_PLLCFGR_DIVP1EN;
286293
RCC->PLL1FRACR = 0;
287294
RCC->PLL1DIVR =
288-
(MICROPY_HW_CLK_PLLN - 1) << RCC_PLL1DIVR_N1_Pos
289-
| (MICROPY_HW_CLK_PLLP - 1) << RCC_PLL1DIVR_P1_Pos // only even P allowed
290-
| (MICROPY_HW_CLK_PLLQ - 1) << RCC_PLL1DIVR_Q1_Pos
291-
| (MICROPY_HW_CLK_PLLR - 1) << RCC_PLL1DIVR_R1_Pos;
295+
(MBOOT_CLK_PLLN - 1) << RCC_PLL1DIVR_N1_Pos
296+
| (MBOOT_CLK_PLLP - 1) << RCC_PLL1DIVR_P1_Pos // only even P allowed
297+
| (MBOOT_CLK_PLLQ - 1) << RCC_PLL1DIVR_Q1_Pos
298+
| (MBOOT_CLK_PLLR - 1) << RCC_PLL1DIVR_R1_Pos;
292299

293300
// Configure PLL3 for use by USB at Q=48MHz
294301
RCC->PLLCKSELR |= MICROPY_HW_CLK_PLL3M << RCC_PLLCKSELR_DIVM3_Pos;
@@ -314,14 +321,14 @@ void SystemClock_Config(void) {
314321
}
315322

316323
// Increase latency before changing SYSCLK
317-
if (MICROPY_HW_FLASH_LATENCY > (FLASH->ACR & FLASH_ACR_LATENCY)) {
318-
__HAL_FLASH_SET_LATENCY(MICROPY_HW_FLASH_LATENCY);
324+
if (MBOOT_FLASH_LATENCY > (FLASH->ACR & FLASH_ACR_LATENCY)) {
325+
__HAL_FLASH_SET_LATENCY(MBOOT_FLASH_LATENCY);
319326
}
320327

321328
// Configure AHB divider
322329
RCC->D1CFGR =
323330
0 << RCC_D1CFGR_D1CPRE_Pos // SYSCLK prescaler of 1
324-
| 8 << RCC_D1CFGR_HPRE_Pos // AHB prescaler of 2
331+
| MBOOT_CLK_AHB_DIV
325332
;
326333

327334
// Configure SYSCLK source from PLL
@@ -330,21 +337,14 @@ void SystemClock_Config(void) {
330337
}
331338

332339
// Decrease latency after changing clock
333-
if (MICROPY_HW_FLASH_LATENCY < (FLASH->ACR & FLASH_ACR_LATENCY)) {
334-
__HAL_FLASH_SET_LATENCY(MICROPY_HW_FLASH_LATENCY);
340+
if (MBOOT_FLASH_LATENCY < (FLASH->ACR & FLASH_ACR_LATENCY)) {
341+
__HAL_FLASH_SET_LATENCY(MBOOT_FLASH_LATENCY);
335342
}
336343

337344
// Set APB clock dividers
338-
RCC->D1CFGR |=
339-
4 << RCC_D1CFGR_D1PPRE_Pos // APB3 prescaler of 2
340-
;
341-
RCC->D2CFGR =
342-
4 << RCC_D2CFGR_D2PPRE2_Pos // APB2 prescaler of 2
343-
| 4 << RCC_D2CFGR_D2PPRE1_Pos // APB1 prescaler of 2
344-
;
345-
RCC->D3CFGR =
346-
4 << RCC_D3CFGR_D3PPRE_Pos // APB4 prescaler of 2
347-
;
345+
RCC->D1CFGR |= MBOOT_CLK_APB3_DIV;
346+
RCC->D2CFGR = MBOOT_CLK_APB2_DIV | MBOOT_CLK_APB1_DIV;
347+
RCC->D3CFGR = MBOOT_CLK_APB4_DIV;
348348

349349
// Update clock value and reconfigure systick now that the frequency changed
350350
SystemCoreClockUpdate();

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