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arch_mips.cpp
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#define _CRT_SECURE_NO_WARNINGS
#define NOMINMAX
#include <inttypes.h>
#include <stdio.h>
#include <string.h>
#include "binaryninjaapi.h"
#include "lowlevelilinstruction.h"
#include "mips.h"
#include "il.h"
using namespace BinaryNinja;
using namespace mips;
using namespace std;
#if defined(_MSC_VER)
#define snprintf _snprintf
#endif
uint32_t bswap32(uint32_t x)
{
return ((x << 24) & 0xff000000 ) |
((x << 8) & 0x00ff0000 ) |
((x >> 8) & 0x0000ff00 ) |
((x >> 24) & 0x000000ff );
}
uint64_t bswap64(uint64_t x)
{
return ((x << 56) & 0xff00000000000000UL) |
((x << 40) & 0x00ff000000000000UL) |
((x << 24) & 0x0000ff0000000000UL) |
((x << 8) & 0x000000ff00000000UL) |
((x >> 8) & 0x00000000ff000000UL) |
((x >> 24) & 0x0000000000ff0000UL) |
((x >> 40) & 0x000000000000ff00UL) |
((x >> 56) & 0x00000000000000ffUL);
}
enum ElfMipsRelocationType : uint32_t
{
R_MIPS_NONE = 0,
R_MIPS_16 = 1,
R_MIPS_32 = 2,
R_MIPS_REL32 = 3,
R_MIPS_26 = 4,
R_MIPS_HI16 = 5,
R_MIPS_LO16 = 6,
R_MIPS_GPREL16 = 7,
R_MIPS_LITERAL = 8,
R_MIPS_GOT16 = 9,
R_MIPS_PC16 = 10,
R_MIPS_CALL16 = 11,
R_MIPS_GPREL32 = 12,
// The remaining relocs are defined on Irix, although they are not
// in the MIPS ELF ABI.
R_MIPS_UNUSED1 = 13,
R_MIPS_UNUSED2 = 14,
R_MIPS_UNUSED3 = 15,
R_MIPS_SHIFT5 = 16,
R_MIPS_SHIFT6 = 17,
R_MIPS_64 = 18,
R_MIPS_GOT_DISP = 19,
R_MIPS_GOT_PAGE = 20,
R_MIPS_GOT_OFST = 21,
//The following two relocation types are specified in the MIPS ABI
//conformance guide version 1.2 but not yet in the psABI.
R_MIPS_GOTHI16 = 22,
R_MIPS_GOTLO16 = 23,
R_MIPS_SUB = 24,
R_MIPS_INSERT_A = 25,
R_MIPS_INSERT_B = 26,
R_MIPS_DELETE = 27,
R_MIPS_HIGHER = 28,
R_MIPS_HIGHEST = 29,
// The following two relocation types are specified in the MIPS ABI
// conformance guide version 1.2 but not yet in the psABI.
R_MIPS_CALLHI16 = 30,
R_MIPS_CALLLO16 = 31,
R_MIPS_SCN_DISP = 32,
R_MIPS_REL16 = 33,
R_MIPS_ADD_IMMEDIATE = 34,
R_MIPS_PJUMP = 35,
R_MIPS_RELGOT = 36,
R_MIPS_JALR = 37,
R_MIPS_TLS_DTPMOD32 = 38, // Module number 32 bit
R_MIPS_TLS_DTPREL32 = 39, // Module-relative offset 32 bit
R_MIPS_TLS_DTPMOD64 = 40, // Module number 64 bit
R_MIPS_TLS_DTPREL64 = 41, // Module-relative offset 64 bit
R_MIPS_TLS_GD = 42, // 16 bit GOT offset for GD
R_MIPS_TLS_LDM = 43, // 16 bit GOT offset for LDM
R_MIPS_TLS_DTPREL_HI16 = 44, // Module-relative offset, high 16 bits
R_MIPS_TLS_DTPREL_LO16 = 45, // Module-relative offset, low 16 bits
R_MIPS_TLS_GOTTPREL = 46, // 16 bit GOT offset for IE
R_MIPS_TLS_TPREL32 = 47, // TP-relative offset, 32 bit
R_MIPS_TLS_TPREL64 = 48, // TP-relative offset, 64 bit
R_MIPS_TLS_TPREL_HI16 = 49, // TP-relative offset, high 16 bits
R_MIPS_TLS_TPREL_LO16 = 50, // TP-relative offset, low 16 bits
R_MIPS_GLOB_DAT = 51,
// This range is reserved for vendor specific relocations.
R_MIPS_LOVENDOR = 100,
R_MIPS64_COPY = 125,
R_MIPS_COPY = 126,
R_MIPS_JUMP_SLOT = 127,
R_MIPS_HIVENDOR = 127
};
static const char* GetRelocationString(ElfMipsRelocationType rel)
{
static map<ElfMipsRelocationType, const char*> relocTable = {
{ R_MIPS_NONE, "R_MIPS_NONE"},
{ R_MIPS_16, "R_MIPS_16"},
{ R_MIPS_32, "R_MIPS_32"},
{ R_MIPS_REL32, "R_MIPS_REL32"},
{ R_MIPS_26, "R_MIPS_26"},
{ R_MIPS_HI16, "R_MIPS_HI16"},
{ R_MIPS_LO16, "R_MIPS_LO16"},
{ R_MIPS_GPREL16, "R_MIPS_GPREL16"},
{ R_MIPS_LITERAL, "R_MIPS_LITERAL"},
{ R_MIPS_GOT16, "R_MIPS_GOT16"},
{ R_MIPS_PC16, "R_MIPS_PC16"},
{ R_MIPS_CALL16, "R_MIPS_CALL16"},
{ R_MIPS_GPREL32, "R_MIPS_GPREL32"},
{ R_MIPS_UNUSED1, "R_MIPS_UNUSED1"},
{ R_MIPS_UNUSED2, "R_MIPS_UNUSED2"},
{ R_MIPS_UNUSED3, "R_MIPS_UNUSED3"},
{ R_MIPS_SHIFT5, "R_MIPS_SHIFT5"},
{ R_MIPS_SHIFT6, "R_MIPS_SHIFT6"},
{ R_MIPS_64, "R_MIPS_64"},
{ R_MIPS_GOT_DISP, "R_MIPS_GOT_DISP"},
{ R_MIPS_GOT_PAGE, "R_MIPS_GOT_PAGE"},
{ R_MIPS_GOT_OFST, "R_MIPS_GOT_OFST"},
{ R_MIPS_GOTHI16, "R_MIPS_GOTHI16"},
{ R_MIPS_GOTLO16, "R_MIPS_GOTLO16"},
{ R_MIPS_SUB, "R_MIPS_SUB"},
{ R_MIPS_INSERT_A, "R_MIPS_INSERT_A"},
{ R_MIPS_INSERT_B, "R_MIPS_INSERT_B"},
{ R_MIPS_DELETE, "R_MIPS_DELETE"},
{ R_MIPS_HIGHER, "R_MIPS_HIGHER"},
{ R_MIPS_HIGHEST, "R_MIPS_HIGHEST"},
{ R_MIPS_CALLHI16, "R_MIPS_CALLHI16"},
{ R_MIPS_CALLLO16, "R_MIPS_CALLLO16"},
{ R_MIPS_SCN_DISP, "R_MIPS_SCN_DISP"},
{ R_MIPS_REL16, "R_MIPS_REL16"},
{ R_MIPS_ADD_IMMEDIATE, "R_MIPS_ADD_IMMEDIATE"},
{ R_MIPS_PJUMP, "R_MIPS_PJUMP"},
{ R_MIPS_RELGOT, "R_MIPS_RELGOT"},
{ R_MIPS_JALR, "R_MIPS_JALR"},
{ R_MIPS_TLS_DTPMOD32, "R_MIPS_TLS_DTPMOD32"},
{ R_MIPS_TLS_DTPREL32, "R_MIPS_TLS_DTPREL32"},
{ R_MIPS_TLS_DTPMOD64, "R_MIPS_TLS_DTPMOD64"},
{ R_MIPS_TLS_DTPREL64, "R_MIPS_TLS_DTPREL64"},
{ R_MIPS_TLS_GD, "R_MIPS_TLS_GD"},
{ R_MIPS_TLS_LDM, "R_MIPS_TLS_LDM"},
{ R_MIPS_TLS_DTPREL_HI16, "R_MIPS_TLS_DTPREL_HI16"},
{ R_MIPS_TLS_DTPREL_LO16, "R_MIPS_TLS_DTPREL_LO16"},
{ R_MIPS_TLS_GOTTPREL, "R_MIPS_TLS_GOTTPREL"},
{ R_MIPS_TLS_TPREL32, "R_MIPS_TLS_TPREL32"},
{ R_MIPS_TLS_TPREL64, "R_MIPS_TLS_TPREL64"},
{ R_MIPS_TLS_TPREL_HI16, "R_MIPS_TLS_TPREL_HI16"},
{ R_MIPS_TLS_TPREL_LO16, "R_MIPS_TLS_TPREL_LO16"},
{ R_MIPS_GLOB_DAT, "R_MIPS_GLOB_DAT"},
{ R_MIPS_LOVENDOR, "R_MIPS_LOVENDOR"},
{ R_MIPS64_COPY, "R_MIPS64_COPY"},
{ R_MIPS_COPY, "R_MIPS_COPY"},
{ R_MIPS_JUMP_SLOT, "R_MIPS_JUMP_SLOT"},
{ R_MIPS_HIVENDOR, "R_MIPS_HIVENDOR"}
};
if (relocTable.count(rel))
return relocTable.at(rel);
return "Unknown MIPS relocation";
}
class MipsArchitecture: public Architecture
{
protected:
size_t m_bits;
BNEndianness m_endian;
MipsVersion version_overwrite;
uint32_t m_decomposeFlags;
virtual bool Disassemble(const uint8_t* data, uint64_t addr, size_t maxLen, Instruction& result)
{
MipsVersion version = version_overwrite;
memset(&result, 0, sizeof(result));
if (m_bits == 64)
{
version = MIPS_64;
}
if (mips_decompose((uint32_t*)data, maxLen, &result, version, addr, m_endian, m_decomposeFlags) != 0)
return false;
return true;
}
virtual size_t GetAddressSize() const override { return m_bits / 8; }
size_t InstructionHasBranchDelay(const Instruction& instr)
{
switch (instr.operation)
{
case MIPS_B:
case MIPS_BAL:
case MIPS_BEQ:
case MIPS_BEQL:
case MIPS_BEQZ:
case MIPS_BGEZ:
case MIPS_BGEZAL:
case MIPS_BGEZALL:
case MIPS_BGEZL:
case MIPS_BGTZ:
case MIPS_BGTZL:
case MIPS_BLEZ:
case MIPS_BLEZL:
case MIPS_BLTZ:
case MIPS_BLTZAL:
case MIPS_BLTZALL:
case MIPS_BLTZL:
case MIPS_BNE:
case MIPS_BNEL:
case MIPS_BNEZ:
case MIPS_JR:
case MIPS_JR_HB:
case MIPS_J:
case MIPS_JAL:
case MIPS_JALR:
case MIPS_JALR_HB:
case MIPS_BC1F:
case MIPS_BC1FL:
case MIPS_BC1T:
case MIPS_BC1TL:
case MIPS_BC2FL:
case MIPS_BC2TL:
case MIPS_BC2F:
case MIPS_BC2T:
case CNMIPS_BBIT0:
case CNMIPS_BBIT032:
case CNMIPS_BBIT1:
case CNMIPS_BBIT132:
return 1;
default:
return 0;
}
}
bool InstructionIsUnalignedMemAccess(const Instruction& instr)
{
switch (instr.operation)
{
case MIPS_LDL:
case MIPS_LDR:
case MIPS_LWL:
case MIPS_LWR:
case MIPS_SDL:
case MIPS_SDR:
case MIPS_SWL:
case MIPS_SWR:
return true;
default:
return false;
}
}
bool IsConditionalBranch(const Instruction& instr)
{
switch (instr.operation)
{
case MIPS_BEQZ:
case MIPS_BGEZ:
case MIPS_BGTZ:
case MIPS_BLEZ:
case MIPS_BLTZ:
case MIPS_BGEZL:
case MIPS_BGTZL:
case MIPS_BLEZL:
case MIPS_BLTZL:
case MIPS_BEQ:
case MIPS_BNE:
case MIPS_BNEZ:
case MIPS_BEQL:
case MIPS_BNEL:
case MIPS_BC1F:
case MIPS_BC1FL:
case MIPS_BC1T:
case MIPS_BC1TL:
case MIPS_BC2FL:
case MIPS_BC2TL:
case MIPS_BC2F:
case MIPS_BC2T:
case CNMIPS_BBIT0:
case CNMIPS_BBIT032:
case CNMIPS_BBIT1:
case CNMIPS_BBIT132:
return true;
default:
return false;
}
}
void SetInstructionInfoForInstruction(uint64_t addr, const Instruction& instr, InstructionInfo& result)
{
result.length = 4;
auto hasBranchDelay = InstructionHasBranchDelay(instr);
switch (instr.operation)
{
//case MIPS_JALX: //This case jumps to a different processor mode microMIPS32/MIPS32/MIPS16e
// break;
//Branch/jump and link immediate
case MIPS_BAL:
if (instr.operands[0].immediate != addr + 8)
result.AddBranch(CallDestination, instr.operands[0].immediate, nullptr, hasBranchDelay);
else
result.delaySlots = 1; // We have a "get pc" mnemonic; do nothing
break;
case MIPS_JAL:
result.AddBranch(CallDestination, instr.operands[0].immediate, nullptr, hasBranchDelay);
break;
//Jmp to register register value is unknown
case MIPS_JALR:
case MIPS_JALR_HB:
result.delaySlots = 1;
break;
case MIPS_BGEZAL:
case MIPS_BLTZAL:
case MIPS_BGEZALL:
case MIPS_BLTZALL:
result.AddBranch(CallDestination, instr.operands[1].immediate, nullptr, hasBranchDelay);
break;
//Unconditional branch and jump
case MIPS_B:
case MIPS_J:
result.AddBranch(UnconditionalBranch, instr.operands[0].immediate, nullptr, hasBranchDelay);
break;
//Conditional branch instructions
case MIPS_BEQZ:
case MIPS_BGEZ:
case MIPS_BGTZ:
case MIPS_BLEZ:
case MIPS_BLTZ:
case MIPS_BNEZ:
case MIPS_BGEZL:
case MIPS_BGTZL:
case MIPS_BLEZL:
case MIPS_BLTZL:
result.AddBranch(TrueBranch, instr.operands[1].immediate, nullptr, hasBranchDelay);
//need to jump over the branch delay slot and current instruction
result.AddBranch(FalseBranch, addr + 8, nullptr, hasBranchDelay);
break;
case MIPS_BEQ:
case MIPS_BNE:
case MIPS_BEQL:
case MIPS_BNEL:
case CNMIPS_BBIT0:
case CNMIPS_BBIT032:
case CNMIPS_BBIT1:
case CNMIPS_BBIT132:
result.AddBranch(TrueBranch, instr.operands[2].immediate, nullptr, hasBranchDelay);
//need to jump over the branch delay slot and current instruction
result.AddBranch(FalseBranch, addr + 8, nullptr, hasBranchDelay);
break;
//Jmp reg isntructions, if they are jumping to the return address register then it is a function return
case MIPS_JR:
case MIPS_JR_HB:
if (instr.operands[0].reg == REG_RA)
result.AddBranch(FunctionReturn, 0, nullptr, hasBranchDelay);
else
result.AddBranch(UnresolvedBranch, 0, nullptr, hasBranchDelay);
break;
case MIPS_BC1F:
case MIPS_BC1FL:
case MIPS_BC1T:
case MIPS_BC1TL:
case MIPS_BC2FL:
case MIPS_BC2TL:
case MIPS_BC2F:
case MIPS_BC2T:
result.AddBranch(TrueBranch, instr.operands[0].immediate, nullptr, hasBranchDelay);
//need to jump over the branch delay slot and current instruction
result.AddBranch(FalseBranch, addr + 8, nullptr, hasBranchDelay);
break;
//Exception return instruction
case MIPS_ERET:
result.AddBranch(FunctionReturn, 0, nullptr, hasBranchDelay);
break;
default:
break;
}
}
public:
MipsArchitecture(const std::string& name, BNEndianness endian, size_t bits, MipsVersion version_in, uint32_t decomposeFlags = 0)
: Architecture(name), m_bits(bits), m_endian(endian), version_overwrite(version_in), m_decomposeFlags(decomposeFlags)
{
Ref<Settings> settings = Settings::Instance();
uint32_t flag_pseudo_ops = settings->Get<bool>("arch.mips.disassembly.pseudoOps") ? DECOMPOSE_FLAGS_PSEUDO_OP : 0;
m_decomposeFlags |= flag_pseudo_ops;
}
virtual BNEndianness GetEndianness() const override
{
return m_endian;
}
virtual size_t GetInstructionAlignment() const override
{
return 4;
}
virtual size_t GetMaxInstructionLength() const override
{
return 8; // To disassemble delay slots, allow two instructions
}
virtual size_t GetOpcodeDisplayLength() const override
{
return 4;
}
virtual bool CanAssemble() override
{
return true;
}
bool Assemble(const string& code, uint64_t addr, DataBuffer& result, string& errors) override
{
(void)addr;
int assembleResult;
char *instrBytes=NULL, *err=NULL;
int instrBytesLen=0, errLen=0;
BNLlvmServicesInit();
errors.clear();
const char* triple = "mips-pc-none-o32";
if (m_endian == LittleEndian)
triple = "mipsel-pc-none-o32";
assembleResult = BNLlvmServicesAssemble(code.c_str(), LLVM_SVCS_DIALECT_UNSPEC,
triple, LLVM_SVCS_CM_DEFAULT, LLVM_SVCS_RM_STATIC,
&instrBytes, &instrBytesLen, &err, &errLen);
if(assembleResult || errLen)
{
errors = err;
BNLlvmServicesAssembleFree(instrBytes, err);
return false;
}
result.Clear();
result.Append(instrBytes, instrBytesLen);
BNLlvmServicesAssembleFree(instrBytes, err);
return true;
}
bool InstructionIsBranchLikely(Instruction& instr)
{
switch (instr.operation)
{
case MIPS_BEQL:
case MIPS_BNEL:
case MIPS_BGTZL:
case MIPS_BGEZL:
case MIPS_BLTZL:
case MIPS_BLEZL:
case MIPS_BC1TL:
case MIPS_BC1FL:
case MIPS_BC2FL:
case MIPS_BC2TL:
case MIPS_BGEZALL:
case MIPS_BLTZALL:
return true;
default:
return false;
}
}
virtual bool GetInstructionLowLevelIL(const uint8_t* data, uint64_t addr, size_t& len, LowLevelILFunction& il) override
{
Instruction instr, secondInstr;
if (!Disassemble(data, addr, len, instr))
{
il.AddInstruction(il.Undefined());
return false;
}
if (InstructionHasBranchDelay(instr) == 1)
{
if (len < 8)
{
LogWarn("Can not lift instruction with delay slot @ 0x%08" PRIx64, addr);
return false;
}
if (!Disassemble(data + instr.size, addr + instr.size, len - instr.size, secondInstr))
{
il.AddInstruction(il.Undefined());
return false;
}
bool status = true;
bool isBranchLikely = InstructionIsBranchLikely(instr);
if (isBranchLikely)
{
InstructionInfo instrInfo;
LowLevelILLabel trueCode, falseCode;
SetInstructionInfoForInstruction(addr, instr, instrInfo);
il.AddInstruction(il.If(GetConditionForInstruction(il, instr, GetAddressSize()), trueCode, falseCode));
il.MarkLabel(trueCode);
il.SetCurrentAddress(this, addr + instr.size);
GetLowLevelILForInstruction(this, addr + instr.size, il, secondInstr, GetAddressSize(), m_decomposeFlags);
for (size_t i = 0; i < instrInfo.branchCount; i++)
{
if (instrInfo.branchType[i] == TrueBranch)
{
BNLowLevelILLabel* trueLabel = il.GetLabelForAddress(this, instrInfo.branchTarget[i]);
if (trueLabel)
il.AddInstruction(il.Goto(*trueLabel));
else
il.AddInstruction(il.Jump(il.ConstPointer(GetAddressSize(), instrInfo.branchTarget[i])));
break;
}
}
il.MarkLabel(falseCode);
}
else
{
size_t nop;
// ensure we have space to preserve one register in case the delay slot
// clobbers a value needed by the branch. this will be eliminated when
// normal LLIL is generated from Lifted IL if we don't need it
il.SetCurrentAddress(this, addr + instr.size);
nop = il.Nop();
il.AddInstruction(nop);
GetLowLevelILForInstruction(this, addr + instr.size, il, secondInstr, GetAddressSize(), m_decomposeFlags);
LowLevelILInstruction delayed;
uint32_t clobbered = BN_INVALID_REGISTER;
size_t instrIdx = il.GetInstructionCount();
if (instrIdx != 0)
{
// FIXME: this assumes that the instruction in the delay slot
// only changed registers in the last IL instruction that it
// added -- strictly speaking we should be starting from the
// first instruction that could have been added and follow all
// paths to the end of that instruction.
delayed = il.GetInstruction(instrIdx - 1);
if ((delayed.operation == LLIL_SET_REG) && (delayed.address == (addr + instr.size)))
clobbered = delayed.GetDestRegister<LLIL_SET_REG>();
}
il.SetCurrentAddress(this, addr);
if ((instr.operation == MIPS_JR) && (instr.operands[0].reg == REG_T9) &&
(secondInstr.operation == MIPS_ADDIU) && (secondInstr.operands[0].reg == REG_SP) &&
(secondInstr.operands[1].reg == REG_SP) && (secondInstr.operands[2].immediate < 0x80000000))
{
il.AddInstruction(il.TailCall(il.Register(4, REG_T9)));
}
else
{
status = GetLowLevelILForInstruction(this, addr, il, instr, GetAddressSize(), m_decomposeFlags);
}
if (clobbered != BN_INVALID_REGISTER)
{
// FIXME: this approach will break with any of the REG_SPLIT operations as well
// any use of partial registers -- this approach needs to be expanded substantially
// to be correct in the general case. also, it uses LLIL_TEMP(1) for the simple reason
// that the mips lifter only uses LLIL_TEMP(0) at the moment.
LowLevelILInstruction lifted = il.GetInstruction(instrIdx);
if ((lifted.operation == LLIL_IF || lifted.operation == LLIL_CALL) && (lifted.address == addr))
{
bool replace = false;
lifted.VisitExprs([&](const LowLevelILInstruction& expr) -> bool {
if (expr.operation == LLIL_REG && expr.GetSourceRegister<LLIL_REG>() == clobbered)
{
// Replace all reads from the clobbered register to a temp register
// that we're going to set (by replacing the earlier nop we added)
il.ReplaceExpr(expr.exprIndex, il.Register(expr.size, LLIL_TEMP(1)));
replace = true;
}
return true;
});
if (replace)
{
// Preserve the value of the clobbered register by replacing the LLIL_NOP
// instruction we added at the beginning with an assignment to the temp
// register we rewrote in the LLIL_IF condition expression
il.SetCurrentAddress(this, addr + instr.size);
il.ReplaceExpr(nop, il.SetRegister(delayed.size, LLIL_TEMP(1), il.Register(delayed.size, delayed.GetDestRegister<LLIL_SET_REG>())));
il.SetCurrentAddress(this, addr);
}
}
}
}
len = instr.size + secondInstr.size;
return status;
}
else if (InstructionIsUnalignedMemAccess(instr) && len >= 8
&& Disassemble(data + 4, addr + 4, len - 4, secondInstr))
{
Instruction* left = nullptr;
Instruction* right = nullptr;
Instruction* base;
uint32_t addrToUse;
bool store = false;
bool proceed = false;
bool is32bit = false;
switch (instr.operation)
{
case MIPS_LDL: proceed = secondInstr.operation == MIPS_LDR; break;
case MIPS_LDR: proceed = secondInstr.operation == MIPS_LDL; break;
case MIPS_LWL: proceed = secondInstr.operation == MIPS_LWR; break;
case MIPS_LWR: proceed = secondInstr.operation == MIPS_LWL; break;
case MIPS_SDL: proceed = secondInstr.operation == MIPS_SDR; break;
case MIPS_SDR: proceed = secondInstr.operation == MIPS_SDL; break;
case MIPS_SWL: proceed = secondInstr.operation == MIPS_SWR; break;
case MIPS_SWR: proceed = secondInstr.operation == MIPS_SWL; break;
default: proceed = false;
}
switch (instr.operation)
{
case MIPS_SDL:
case MIPS_SDR:
case MIPS_SWL:
case MIPS_SWR:
store = true;
break;
case MIPS_LDL:
case MIPS_LDR:
case MIPS_LWL:
case MIPS_LWR:
store = false;
break;
default: proceed = false;
}
switch (instr.operation)
{
case MIPS_LDL:
case MIPS_LWL:
case MIPS_SDL:
case MIPS_SWL:
left = &instr;
right = &secondInstr;
break;
case MIPS_LDR:
case MIPS_LWR:
case MIPS_SDR:
case MIPS_SWR:
left = &secondInstr;
right = &instr;
break;
default: proceed = false;
}
switch (instr.operation)
{
case MIPS_LWL:
case MIPS_LWR:
case MIPS_SWL:
case MIPS_SWR:
is32bit = true;
break;
case MIPS_LDL:
case MIPS_LDR:
case MIPS_SDL:
case MIPS_SDR:
is32bit = false;
break;
default: proceed = false;
}
proceed = proceed && (instr.operands[0].reg == secondInstr.operands[0].reg);
if (m_endian == BigEndian)
{
if (is32bit)
{
proceed = proceed && ((left->operands[1].immediate + 3) == right->operands[1].immediate);
addrToUse = (uint32_t)addr + ((&instr == left) ? 0 : 4);
}
else
{
proceed = proceed && ((left->operands[1].immediate + 7) == right->operands[1].immediate);
addrToUse = (uint32_t)addr + ((&instr == left) ? 0 : 8);
}
base = left;
}
else
{
if (is32bit)
{
proceed = proceed && (left->operands[1].immediate == (right->operands[1].immediate + 3));
addrToUse = (uint32_t)addr + ((&instr == right) ? 0 : 4);
}
else
{
proceed = proceed && (left->operands[1].immediate == (right->operands[1].immediate + 7));
addrToUse = (uint32_t)addr + ((&instr == right) ? 0 : 8);
}
base = right;
}
if (proceed)
{
len = 8;
il.SetCurrentAddress(this, addrToUse);
if (store)
base->operation = is32bit ? MIPS_SW : MIPS_SD;
else
base->operation = is32bit ? MIPS_LW : MIPS_LD;
return GetLowLevelILForInstruction(this, addrToUse, il, *base, GetAddressSize(), m_decomposeFlags);
}
}
len = instr.size;
return GetLowLevelILForInstruction(this, addr, il, instr, GetAddressSize(), m_decomposeFlags);
}
virtual bool GetInstructionInfo(const uint8_t* data, uint64_t addr, size_t maxLen, InstructionInfo& result) override
{
if (maxLen < 4)
return false;
Instruction instr;
if (!Disassemble(data, addr, maxLen, instr))
return false;
SetInstructionInfoForInstruction(addr, instr, result);
return true;
}
virtual bool GetInstructionText(const uint8_t* data, uint64_t addr, size_t& len, vector<InstructionTextToken>& result) override
{
Instruction instr;
char operand[64];
char padding[9];
const char* reg = NULL;
if (!Disassemble(data, addr, len, instr))
return false;
len = instr.size;
memset(padding, 0x20, sizeof(padding));
const char* operation = get_operation(instr.operation);
if (operation == NULL)
return false;
size_t operationLen = strlen(operation);
if (operationLen < 8)
{
padding[8-operationLen] = '\0';
}
else
padding[1] = '\0';
result.emplace_back(InstructionToken, operation);
result.emplace_back(TextToken, padding);
for (size_t i = 0; i < MAX_OPERANDS; i++)
{
if (instr.operands[i].operandClass == NONE)
return true;
int32_t imm = instr.operands[i].immediate;
uint64_t label_imm = instr.operands[i].immediate;
if (i != 0)
result.emplace_back(OperandSeparatorToken, ", ");
switch (instr.operands[i].operandClass)
{
case IMM:
if (imm < -9)
snprintf(operand, sizeof(operand), "-%#x", -imm);
else if (imm < 0)
snprintf(operand, sizeof(operand), "-%d", -imm);
else if (imm < 10)
snprintf(operand, sizeof(operand), "%d", imm);
else
snprintf(operand, sizeof(operand), "%#x", imm);
result.emplace_back(IntegerToken, operand, imm);
break;
case LABEL:
snprintf(operand, sizeof(operand), "%#" PRIx64, label_imm);
result.emplace_back(PossibleAddressToken, operand, imm);
break;
case REG:
reg = get_register((Reg)instr.operands[i].reg);
if (reg == NULL)
{
return false;
}
result.emplace_back(RegisterToken, reg);
break;
case FLAG:
reg = get_flag((Flag)instr.operands[i].reg);
if (reg == NULL)
{
return false;
}
result.push_back(InstructionTextToken(RegisterToken, reg));
break;
case HINT:
reg = get_hint((Hint)instr.operands[i].reg);
if (reg == NULL)
{
return false;
}
result.emplace_back(RegisterToken, reg);
break;
case MEM_IMM:
result.emplace_back(BeginMemoryOperandToken, "");
if (imm < -9)
snprintf(operand, sizeof(operand), "-%#x", -imm);
else if (imm < 0)
snprintf(operand, sizeof(operand), "-%d", -imm);
else if (imm < 10)
snprintf(operand, sizeof(operand), "%d", imm);
else
snprintf(operand, sizeof(operand), "%#x", imm);
result.emplace_back(IntegerToken, operand, imm);
if (instr.operands[i].reg == REG_ZERO)
break;
result.emplace_back(BraceToken, "(");
reg = get_register((Reg)instr.operands[i].reg);
if (reg == NULL)
return false;
result.emplace_back(RegisterToken, reg);
result.emplace_back(BraceToken, ")");
result.emplace_back(EndMemoryOperandToken, "");
break;
case MEM_REG:
result.emplace_back(BeginMemoryOperandToken, "");
reg = get_register((Reg)imm);
if (reg == NULL)
return false;
result.emplace_back(RegisterToken, reg);
result.emplace_back(BraceToken, "(");
reg = get_register((Reg)instr.operands[i].reg);
if (reg == NULL)
return false;
result.emplace_back(RegisterToken, reg);
result.emplace_back(BraceToken, ")");
result.emplace_back(EndMemoryOperandToken, "");
break;
default:
LogError("operandClass %x\n", instr.operands[i].operandClass);
return false;
}
}
return true;
}
virtual string GetIntrinsicName(uint32_t intrinsic) override
{
switch (intrinsic)
{
case MIPS_INTRIN_WSBH:
return "__wsbh";
case MIPS_INTRIN_DSBH:
return "_dsbh";
case MIPS_INTRIN_DSHD:
return "_dshd";
case MIPS_INTRIN_MFC0:
return "moveFromCoprocessor0";
case MIPS_INTRIN_MFC2:
return "moveFromCoprocessor2";
case MIPS_INTRIN_MFC_UNIMPLEMENTED:
return "moveFromCoprocessorUnimplemented";
case MIPS_INTRIN_MTC0:
return "moveToCoprocessor0";
case MIPS_INTRIN_MTC2:
return "moveToCoprocessor2";
case MIPS_INTRIN_MTC_UNIMPLEMENTED:
return "moveToCoprocessorUnimplemented";
case MIPS_INTRIN_DMFC0:
return "moveDwordFromCoprocessor0";
case MIPS_INTRIN_DMFC2:
return "moveDwordFromCoprocessor2";
case MIPS_INTRIN_DMFC_UNIMPLEMENTED:
return "moveDwordFromCoprocessorUnimplemented";
case MIPS_INTRIN_DMTC0:
return "moveDwordToCoprocessor0";
case MIPS_INTRIN_DMTC2:
return "moveDwordToCoprocessor2";
case MIPS_INTRIN_DMTC_UNIMPLEMENTED:
return "moveDwordToCoprocessorUnimplemented";
case MIPS_INTRIN_SYNC:
return "_sync";
case MIPS_INTRIN_SYNCI:
return "_SynchronizeCacheLines";
case MIPS_INTRIN_EI:
return "_enableInterrupts";
case MIPS_INTRIN_DI:
return "_disableInterrupts";
case MIPS_INTRIN_EHB:
return "_clearExecutionHazards";
case MIPS_INTRIN_WAIT:
return "_enterLowPowerMode";
case MIPS_INTRIN_PAUSE:
return "_waitForLLbitClear";
case MIPS_INTRIN_HWR0:
return "_cpuNum";
case MIPS_INTRIN_HWR1:
return "_synciStep";
case MIPS_INTRIN_HWR2:
return "_cycleCounter";
case MIPS_INTRIN_HWR3:
return "_cycleCounterResolution";
case MIPS_INTRIN_HWR29:
return "_userLocalRegister";
case MIPS_INTRIN_HWR_UNKNOWN:
return "_hardwareRegister";
case MIPS_INTRIN_LLBIT_SET:
return "_setLLBit";
case MIPS_INTRIN_LLBIT_CHECK:
return "_checkLLBit";
case MIPS_INTRIN_PREFETCH:
return "_prefetch";
case MIPS_INTRIN_CACHE:
return "_cache";
case MIPS_INTRIN_SDBBP:
return "_softwareDebugBreakpoint";
case MIPS_INTRIN_GET_LEFT_PART32:
return "_getLeftPart32";
case MIPS_INTRIN_GET_RIGHT_PART32:
return "_getRightPart32";
case MIPS_INTRIN_SET_LEFT_PART32:
return "_setLeftPart32";
case MIPS_INTRIN_SET_RIGHT_PART32:
return "_setRightPart32";
case MIPS_INTRIN_GET_LEFT_PART64:
return "_getLeftPart64";
case MIPS_INTRIN_GET_RIGHT_PART64:
return "_getRightPart64";
case MIPS_INTRIN_SET_LEFT_PART64:
return "_setLeftPart64";
case MIPS_INTRIN_SET_RIGHT_PART64:
return "_setRightPart64";
case MIPS_INTRIN_TLBSET:
return "_writeTLB";
case MIPS_INTRIN_TLBGET:
return "_readTLB";
case MIPS_INTRIN_TLBSEARCH:
return "_probeTLB";
case MIPS_INTRIN_TLBINV:
return "_invalidateTLB";
case MIPS_INTRIN_TLBINVF:
return "_invalidateTLBFlush";
case CNMIPS_INTRIN_SYNCIOBDMA:
return "_synciobdma";
case CNMIPS_INTRIN_SYNCS:
return "_syncs";
case CNMIPS_INTRIN_SYNCW:
return "_syncw";
case CNMIPS_INTRIN_SYNCWS:
return "_syncws";
case CNMIPS_INTRIN_HWR30:
return "_chOrd";
case CNMIPS_INTRIN_HWR31:
return "_cvmCount";