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Add/test support for RISC-V #35
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Testing with MicroPython v1.24.0-542-g9ee2ef510 Most of the modules, such as
A couple of modules, such as eml_iir_q15, pass the linker - but then fail with mpy-cross. Presumably this is because we have some Python code that is to be embedded in the module. And it seems this is not supported on rv32imc at the moment
So this will require some work upstream in MicroPython to get working |
In the short, term in might be that #18 is the way forward |
On Arch Linux, the rv32imc GCC compiler has a different name than what |
This could now be re-tested using the newly added support for building as external C modules. https://emlearn-micropython.readthedocs.io/en/latest/external_modules.html But I am also hoping that dynamic native modules will be possible, so I am keeping this open at least until we have managed to file issues upstream in MicroPython and heard back about that. |
Please refer to my issue, micropython/micropython#17046
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It seems that the natmod support for RISC-V architecture may have gotten into a useful place now in MicroPython after 1.24. This is the architecture used by chips such as ESP32-C3, ESP32-C6
This should be possible by doing a build with
ARCH=rv32imc
.We also need to set up the relevant toolchain on CI to automate the builds.
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