diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..4fd4127 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "vendor/wb-modules"] + path = vendor/wb-modules + url = https://github.com/HoneyGol-Microsystems/wb-modules diff --git a/README.md b/README.md index e293ebf..89ed18b 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,14 @@ +# riscv-dbg VESP fork +This fork is intented to be used with VESP CPU cores. Wishbone translation layer from ibex_wb is adopted. +There are 4 FuseSoC cores: +- riscv-dbg: common base RTL +- riscv-dbg-tb: simulation RTL +- riscv-dbg-bscane: top core, Wishbone+BSCANE2 interfaces +- riscv-dbg-jtag: top core, Wishbone+JTAG interfaces + +For synthesis, pick either riscv-dbg-bscane or riscv-dbg-jtag. For simulation, riscv-dbg-jtag and riscv-dbg-tb are required. These cores depend on [wb-modules](https://github.com/HoneyGol-Microsystems/wb-modules) and [PULP common cells](https://github.com/HoneyGol-Microsystems/pulp_common_cells). + +Original README follows... # RISC-V Debug Support for various Cores This module is an implementation of a debug unit compliant with the [RISC-V diff --git a/riscv-dbg-bscane.core b/riscv-dbg-bscane.core new file mode 100644 index 0000000..d800bba --- /dev/null +++ b/riscv-dbg-bscane.core @@ -0,0 +1,17 @@ +CAPI=2: +name: pulp-platform:ip:riscv-dbg-bscane:1.0.0 +description: PULP RISC-V Debug Modules, Xilinx BSCANE version + +filesets: + rtl: + files: + - src/dmi_bscane_tap.sv + file_type: systemVerilogSource + depend: + - pulp-platform:ip:riscv-dbg-common + +targets: + default: &default + filesets: + - rtl + toplevel: dummy diff --git a/riscv-dbg-jtag.core b/riscv-dbg-jtag.core new file mode 100644 index 0000000..f5697f9 --- /dev/null +++ b/riscv-dbg-jtag.core @@ -0,0 +1,17 @@ +CAPI=2: +name: pulp-platform:ip:riscv-dbg-jtag:1.0.0 +description: PULP RISC-V Debug Modules, JTAG version + +filesets: + rtl: + files: + - src/dmi_jtag_tap.sv + file_type: systemVerilogSource + depend: + - pulp-platform:ip:riscv-dbg-common + +targets: + default: &default + filesets: + - rtl + toplevel: dummy diff --git a/riscv-dbg-tb.core b/riscv-dbg-tb.core new file mode 100644 index 0000000..6359869 --- /dev/null +++ b/riscv-dbg-tb.core @@ -0,0 +1,17 @@ +CAPI=2: +name: pulp-platform:ip:riscv-dbg-tb:1.0.0 +description: PULP RISC-V Debug Modules, verification modules + +filesets: + rtl: + files: + - src/dm_pkg.sv + - src/dmi_test.sv + - tb/SimJTAG.sv + file_type: systemVerilogSource + +targets: + default: &default + filesets: + - rtl + toplevel: dummy diff --git a/riscv-dbg.core b/riscv-dbg.core new file mode 100644 index 0000000..2f16805 --- /dev/null +++ b/riscv-dbg.core @@ -0,0 +1,32 @@ +CAPI=2: +name: pulp-platform:ip:riscv-dbg-common:1.0.0 +description: PULP RISC-V Debug Modules Common + +filesets: + rtl: + files: + - src/tc_clk.sv + - src/dm_pkg.sv + - src/dmi_intf.sv + - src/dm_csrs.sv + - debug_rom/debug_rom.sv + - debug_rom/debug_rom_one_scratch.sv + - src/dm_mem.sv + - src/dmi_cdc.sv + - src/dmi_jtag.sv + - src/dm_sba.sv + - src/dm_top.sv + - wb/ibex_core_if.sv + - wb/ibexm2wbs.sv + - wb/ibexs2wbm.sv + - wb/wb_dm_top.sv + file_type: systemVerilogSource + depend: + - hgm:vesp-ip:wb-modules + - pulp-platform.org::common_cells:1.37.0 + +targets: + default: &default + filesets: + - rtl + toplevel: dummy diff --git a/src/tc_clk.sv b/src/tc_clk.sv new file mode 100644 index 0000000..d5322cf --- /dev/null +++ b/src/tc_clk.sv @@ -0,0 +1,120 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module tc_clk_and2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i & clk1_i; + +endmodule + +module tc_clk_buffer ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +// Description: Behavioral model of an integrated clock-gating cell (ICG) +module tc_clk_gating #( + /// This paramaeter is a hint for tool/technology specific mappings of this + /// tech_cell. It indicates wether this particular clk gate instance is + /// required for functional correctness or just instantiated for power + /// savings. If IS_FUNCTIONAL == 0, technology specific mappings might + /// replace this cell with a feedthrough connection without any gating. + parameter bit IS_FUNCTIONAL = 1'b1 +)( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o +); + + logic clk_en; + + always_latch begin + if (clk_i == 1'b0) clk_en <= en_i | test_en_i; + end + + assign clk_o = clk_i & clk_en; + +endmodule + +module tc_clk_inverter ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = ~clk_i; + +endmodule + +// Warning: Typical clock mux cells of a technologies std cell library ARE NOT +// GLITCH FREE!! The only difference to a regular multiplexer cell is that they +// feature balanced rise- and fall-times. In other words: SWITCHING FROM ONE +// CLOCK TO THE OTHER CAN INTRODUCE GLITCHES. ALSO, GLITCHES ON THE SELECT LINE +// DIRECTLY TRANSLATE TO GLITCHES ON THE OUTPUT CLOCK!! This cell is only +// intended to be used for quasi-static switching between clocks when one of the +// clocks is anyway inactive or if the downstream logic remains gated or in +// reset state during the transition phase. If you need dynamic switching +// between arbitrary input clocks without introducing glitches, have a look at +// the clk_mux_glitch_free cell in the pulp-platform/common_cells repository. +module tc_clk_mux2 ( + input logic clk0_i, + input logic clk1_i, + input logic clk_sel_i, + output logic clk_o +); + + assign clk_o = (clk_sel_i) ? clk1_i : clk0_i; + +endmodule + +module tc_clk_xor2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i ^ clk1_i; + +endmodule + +module tc_clk_or2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i | clk1_i; + +endmodule + +`ifndef SYNTHESIS +module tc_clk_delay #( + parameter int unsigned Delay = 300ps +) ( + input logic in_i, + output logic out_o +); + +// pragma translate_off +`ifndef VERILATOR + assign #(Delay) out_o = in_i; +`endif +// pragma translate_on + +endmodule +`endif \ No newline at end of file diff --git a/tb/dm_debug.cfg b/tb/dm_debug.cfg index 1ac2555..800cc5d 100644 --- a/tb/dm_debug.cfg +++ b/tb/dm_debug.cfg @@ -1,10 +1,11 @@ -debug_level 4 +# debug_level 4 adapter_khz 10000 interface remote_bitbang remote_bitbang_host localhost remote_bitbang_port $::env(JTAG_VPI_PORT) +gdb_port 3333 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3 @@ -15,7 +16,8 @@ foreach t [jtag names] { set _TARGETNAME $_CHIPNAME.cpu #target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x3e0 -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv +# target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv +target create $_TARGETNAME riscv -chain-position $_TARGETNAME riscv set_reset_timeout_sec 2000 riscv set_command_timeout_sec 2000 diff --git a/vendor/wb-modules b/vendor/wb-modules new file mode 160000 index 0000000..acc6fcb --- /dev/null +++ b/vendor/wb-modules @@ -0,0 +1 @@ +Subproject commit acc6fcb56ec1fecbcd1d0beec6ed30bf9e098ca4 diff --git a/wb/LICENSE b/wb/LICENSE new file mode 100644 index 0000000..f49a4e1 --- /dev/null +++ b/wb/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. \ No newline at end of file diff --git a/wb/README.md b/wb/README.md new file mode 100644 index 0000000..5602942 --- /dev/null +++ b/wb/README.md @@ -0,0 +1,2 @@ +# riscv-dbg WB compatibility layer +These sources were adopted from the [ibex_wb project](https://github.com/pbing/ibex_wb/tree/master) licensed under the Apache 2.0 license. \ No newline at end of file diff --git a/wb/ibex_core_if.sv b/wb/ibex_core_if.sv new file mode 100644 index 0000000..7bdba4d --- /dev/null +++ b/wb/ibex_core_if.sv @@ -0,0 +1,59 @@ +/* Core interface */ + +`default_nettype none + +interface ibex_core_if + (input wire clk, + input wire rst_n); + + logic req; + logic gnt; + logic rvalid; + logic we; + logic [3:0] be; + logic [31:0] addr; + logic [31:0] wdata; + logic [31:0] rdata; + logic err; + + modport master + (input clk, + input rst_n, + output req, + input gnt, + input rvalid, + output we, + output be, + output addr, + output wdata, + input rdata, + input err); + + modport slave + (input clk, + input rst_n, + input req, + output gnt, + output rvalid, + input we, + input be, + input addr, + input wdata, + output rdata, + output err); + + modport monitor + (input clk, + input rst_n, + input req, + input gnt, + input rvalid, + input we, + input be, + input addr, + input wdata, + input rdata, + input err); +endinterface + +`resetall \ No newline at end of file diff --git a/wb/ibexm2wbs.sv b/wb/ibexm2wbs.sv new file mode 100644 index 0000000..20fed4a --- /dev/null +++ b/wb/ibexm2wbs.sv @@ -0,0 +1,29 @@ +/* Converter between DM slave interface and Wishbone interface */ + +`default_nettype none + +// Ibex master to Wishbone slave converter. +module ibexm2wbs + (ibex_core_if.master slave, + wishbone_p_if.slave wb); + + logic valid; + + assign valid = wb.cyc & wb.stb; + assign slave.req = valid; + assign slave.we = wb.we; + assign slave.addr = wb.adr; + assign slave.be = wb.sel; + assign slave.wdata = wb.dat_i; + assign wb.dat_o = slave.rdata; + assign wb.stall = ~slave.gnt; + assign wb.err = slave.err; + + always_ff @(posedge wb.clk_i or posedge wb.rst_i) + if (wb.rst_i) + wb.ack <= 1'b0; + else + wb.ack <= valid & ~wb.stall; +endmodule + +`resetall \ No newline at end of file diff --git a/wb/ibexs2wbm.sv b/wb/ibexs2wbm.sv new file mode 100644 index 0000000..fdb84b2 --- /dev/null +++ b/wb/ibexs2wbm.sv @@ -0,0 +1,34 @@ +/* Converter between Ibex core interface and Wishbone interface */ + +`default_nettype none + +// Ibex slave to Wishbone master converter. +module ibexs2wbm + (ibex_core_if.slave core, + wishbone_p_if.master wb); + + logic cyc; + + assign core.gnt = core.req & ~wb.stall; + assign core.rvalid = wb.ack; + assign core.err = wb.err; + assign core.rdata = wb.dat_i; + assign wb.stb = core.req; + assign wb.adr = core.addr; + assign wb.dat_o = core.wdata; + assign wb.we = core.we; + assign wb.sel = core.we ? core.be : '1; + + always_ff @(posedge wb.clk_i or posedge wb.rst_i) + if (wb.rst_i) + cyc <= 1'b0; + else + if (core.req) + cyc <= 1'b1; + else if (wb.ack || wb.err) + cyc <= 1'b0; + + assign wb.cyc = core.req | cyc; +endmodule + +`resetall \ No newline at end of file diff --git a/wb/wb_dm_top.sv b/wb/wb_dm_top.sv new file mode 100644 index 0000000..43210f0 --- /dev/null +++ b/wb/wb_dm_top.sv @@ -0,0 +1,99 @@ +/* RISC-V debug module with Wishbone interface */ + +`default_nettype none + +module wb_dm_top + #(parameter int NrHarts = 1, + parameter int BusWidth = 32, + parameter logic [NrHarts-1:0] SelectableHarts = 1, // Bitmask to select physically available harts for systems that don't use hart numbers in a contiguous fashion. + parameter int unsigned DmBaseAddress = 'h1000 // default to non-zero page + ) ( + input wire clk, // clock + input wire rst_n, // asynchronous reset active low, connect PoR here, not the system reset + input wire testmode, + output logic ndmreset, // non-debug module reset + input wire logic ndmreset_ack, // non-debug module reset ack + output logic dmactive, // debug module is active + output logic [NrHarts-1:0] debug_req, // async debug request + input wire [NrHarts-1:0] unavailable, // communicate whether the hart is unavailable (e.g.: power down) + input wire dm::hartinfo_t [NrHarts-1:0] hartinfo, + + /* Wishbone interfaces */ + wishbone_p_if.slave wbs, + wishbone_p_if.master wbm, + + /* Connection to DTM - compatible to RocketChip Debug Module */ + input wire dmi_rst_n, + input wire dmi_req_valid, + output logic dmi_req_ready, + input /*wire*/ dm::dmi_req_t dmi_req, + + output logic dmi_resp_valid, + input wire dmi_resp_ready, + output dm::dmi_resp_t dmi_resp); + + logic slave_req; + logic slave_we; + logic [BusWidth-1:0] slave_addr; + logic [BusWidth/8-1:0] slave_be; + logic [BusWidth-1:0] slave_wdata; + logic [BusWidth-1:0] slave_rdata; + + ibex_core_if slave_core(.*); + ibex_core_if master_core(.*); + + dm_top + #(.NrHarts (NrHarts), + .BusWidth(BusWidth), + .SelectableHarts(SelectableHarts), + .DmBaseAddress(DmBaseAddress)) + inst_dm_top + (.clk_i (clk), + .rst_ni (rst_n), + .testmode_i (testmode), + .ndmreset_o (ndmreset), + .ndmreset_ack_i (ndmreset_ack), + .dmactive_o (dmactive), + .debug_req_o (debug_req), + .unavailable_i (unavailable), + .hartinfo_i (hartinfo), + + .slave_req_i (slave_core.req), + .slave_we_i (slave_core.we), + .slave_addr_i (slave_core.addr), + .slave_be_i (slave_core.be), + .slave_wdata_i (slave_core.wdata), + .slave_rdata_o (slave_core.rdata), + + .master_req_o (master_core.req), + .master_add_o (master_core.addr), + .master_we_o (master_core.we), + .master_wdata_o (master_core.wdata), + .master_be_o (master_core.be), + .master_gnt_i (master_core.gnt), + .master_r_valid_i (master_core.rvalid), + .master_r_rdata_i (master_core.rdata), + + .dmi_rst_ni (dmi_rst_n), + .dmi_req_valid_i (dmi_req_valid), + .dmi_req_ready_o (dmi_req_ready), + .dmi_req_i (dmi_req), + .dmi_resp_valid_o (dmi_resp_valid), + .dmi_resp_ready_i (dmi_resp_ready), + .dmi_resp_o (dmi_resp)); + + /* Wishbone */ + assign slave_core.gnt = 1'b1; + assign slave_core.rvalid = 1'b0; // don't care + assign slave_core.err = 1'b0; + + ibexm2wbs slave_core2wb + (.slave (slave_core), + .wb (wbs)); + + ibexs2wbm master_core2wb + (.core (master_core), + .wb (wbm)); +endmodule + +`resetall \ No newline at end of file