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# pyOCD debugger
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- # Copyright (c) 2018-2019 Arm Limited
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+ # Copyright (c) 2018-2020 Arm Limited
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# SPDX-License-Identifier: Apache-2.0
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
@@ -43,15 +43,20 @@ class Protocol(Enum):
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# 8-bit transfers have a maximum size of the maximum USB packet size (64 bytes for full speed).
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MAXIMUM_TRANSFER_SIZE = 1024
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- ## Minimum required STLink firmware version.
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+ ## Minimum required STLink firmware version (hw version 2) .
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MIN_JTAG_VERSION = 24
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- ## Firmware version that adds 16-bit transfers.
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+ ## Firmware version that adds 16-bit transfers (hw version 2) .
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MIN_JTAG_VERSION_16BIT_XFER = 26
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- ## Firmware version that adds multiple AP support.
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+ ## Firmware version that adds multiple AP support (hw version 2) .
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MIN_JTAG_VERSION_MULTI_AP = 28
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+ ## Firmware version that adds DP bank support.
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+ #
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+ # Keys are the hardware version, value is the minimum JTAG version.
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+ MIN_JTAG_VERSION_DPBANKSEL = {2 : 32 , 3 : 2 }
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+
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## Port number to use to indicate DP registers.
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DP_PORT = 0xffff
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@@ -176,6 +181,14 @@ def version_str(self):
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@property
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def target_voltage (self ):
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return self ._target_voltage
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+
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+ @property
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+ def supports_banked_dp (self ):
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+ """! @brief Whether the firmware version supports accessing banked DP registers.
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+
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+ This property is not valid until the connection is opened.
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+ """
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+ return self ._jtag_version >= self .MIN_JTAG_VERSION_DPBANKSEL_HW_V2 [self ._hw_version ]
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def get_target_voltage (self ):
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response = self ._device .transfer ([Commands .GET_TARGET_VOLTAGE ], readSize = 8 )
@@ -402,10 +415,20 @@ def read_mem8(self, addr, size, apsel):
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def write_mem8 (self , addr , data , apsel ):
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self ._write_mem (addr , data , Commands .JTAG_WRITEMEM_8BIT , self ._device .max_packet_size , apsel )
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+ def _check_dp_bank (self , port , addr ):
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+ """! @brief Check if attempting to access a banked DP register with a firmware version that
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+ doesn't support that.
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+ """
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+ if ((port == self .DP_PORT ) and ((addr & 0xf0 ) != 0 ) and not self .supports_banked_dp ):
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+ raise exceptions .ProbeError ("this STLinkV%d firmware version does not support accessing"
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+ " banked DP registers; please upgrade to the latest STLinkV%d firmware release" ,
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+ self ._hw_version , self ._hw_version )
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+
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def read_dap_register (self , port , addr ):
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- assert ((addr & 0xf0 ) == 0 ) or (port != self .DP_PORT ), "banks are not allowed for DP registers"
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assert (addr >> 16 ) == 0 , "register address must be 16-bit"
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+ self ._check_dp_bank (port , addr )
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+
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with self ._lock :
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cmd = [Commands .JTAG_COMMAND , Commands .JTAG_READ_DAP_REG ]
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cmd .extend (six .iterbytes (struct .pack ('<HH' , port , addr )))
@@ -415,9 +438,10 @@ def read_dap_register(self, port, addr):
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return value
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def write_dap_register (self , port , addr , value ):
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- assert ((addr & 0xf0 ) == 0 ) or (port != self .DP_PORT ), "banks are not allowed for DP registers"
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assert (addr >> 16 ) == 0 , "register address must be 16-bit"
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+ self ._check_dp_bank (port , addr )
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+
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with self ._lock :
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cmd = [Commands .JTAG_COMMAND , Commands .JTAG_WRITE_DAP_REG ]
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cmd .extend (six .iterbytes (struct .pack ('<HHI' , port , addr , value )))
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