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STLink: support banked DP registers in protocol layer.
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+30
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pyocd/probe/stlink/stlink.py

Lines changed: 30 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# pyOCD debugger
2-
# Copyright (c) 2018-2019 Arm Limited
2+
# Copyright (c) 2018-2020 Arm Limited
33
# SPDX-License-Identifier: Apache-2.0
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
@@ -43,15 +43,20 @@ class Protocol(Enum):
4343
# 8-bit transfers have a maximum size of the maximum USB packet size (64 bytes for full speed).
4444
MAXIMUM_TRANSFER_SIZE = 1024
4545

46-
## Minimum required STLink firmware version.
46+
## Minimum required STLink firmware version (hw version 2).
4747
MIN_JTAG_VERSION = 24
4848

49-
## Firmware version that adds 16-bit transfers.
49+
## Firmware version that adds 16-bit transfers (hw version 2).
5050
MIN_JTAG_VERSION_16BIT_XFER = 26
5151

52-
## Firmware version that adds multiple AP support.
52+
## Firmware version that adds multiple AP support (hw version 2).
5353
MIN_JTAG_VERSION_MULTI_AP = 28
5454

55+
## Firmware version that adds DP bank support.
56+
#
57+
# Keys are the hardware version, value is the minimum JTAG version.
58+
MIN_JTAG_VERSION_DPBANKSEL = {2: 32, 3: 2}
59+
5560
## Port number to use to indicate DP registers.
5661
DP_PORT = 0xffff
5762

@@ -176,6 +181,14 @@ def version_str(self):
176181
@property
177182
def target_voltage(self):
178183
return self._target_voltage
184+
185+
@property
186+
def supports_banked_dp(self):
187+
"""! @brief Whether the firmware version supports accessing banked DP registers.
188+
189+
This property is not valid until the connection is opened.
190+
"""
191+
return self._jtag_version >= self.MIN_JTAG_VERSION_DPBANKSEL_HW_V2[self._hw_version]
179192

180193
def get_target_voltage(self):
181194
response = self._device.transfer([Commands.GET_TARGET_VOLTAGE], readSize=8)
@@ -402,10 +415,20 @@ def read_mem8(self, addr, size, apsel):
402415
def write_mem8(self, addr, data, apsel):
403416
self._write_mem(addr, data, Commands.JTAG_WRITEMEM_8BIT, self._device.max_packet_size, apsel)
404417

418+
def _check_dp_bank(self, port, addr):
419+
"""! @brief Check if attempting to access a banked DP register with a firmware version that
420+
doesn't support that.
421+
"""
422+
if ((port == self.DP_PORT) and ((addr & 0xf0) != 0) and not self.supports_banked_dp):
423+
raise exceptions.ProbeError("this STLinkV%d firmware version does not support accessing"
424+
" banked DP registers; please upgrade to the latest STLinkV%d firmware release",
425+
self._hw_version, self._hw_version)
426+
405427
def read_dap_register(self, port, addr):
406-
assert ((addr & 0xf0) == 0) or (port != self.DP_PORT), "banks are not allowed for DP registers"
407428
assert (addr >> 16) == 0, "register address must be 16-bit"
408429

430+
self._check_dp_bank(port, addr)
431+
409432
with self._lock:
410433
cmd = [Commands.JTAG_COMMAND, Commands.JTAG_READ_DAP_REG]
411434
cmd.extend(six.iterbytes(struct.pack('<HH', port, addr)))
@@ -415,9 +438,10 @@ def read_dap_register(self, port, addr):
415438
return value
416439

417440
def write_dap_register(self, port, addr, value):
418-
assert ((addr & 0xf0) == 0) or (port != self.DP_PORT), "banks are not allowed for DP registers"
419441
assert (addr >> 16) == 0, "register address must be 16-bit"
420442

443+
self._check_dp_bank(port, addr)
444+
421445
with self._lock:
422446
cmd = [Commands.JTAG_COMMAND, Commands.JTAG_WRITE_DAP_REG]
423447
cmd.extend(six.iterbytes(struct.pack('<HHI', port, addr, value)))

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