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| 1 | +# pyOCD debugger |
| 2 | +# Copyright (c) 2020 Cypress Semiconductor Corporation |
| 3 | +# SPDX-License-Identifier: Apache-2.0 |
| 4 | +# |
| 5 | +# Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | +# you may not use this file except in compliance with the License. |
| 7 | +# You may obtain a copy of the License at |
| 8 | +# |
| 9 | +# http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | +# |
| 11 | +# Unless required by applicable law or agreed to in writing, software |
| 12 | +# distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | +# See the License for the specific language governing permissions and |
| 15 | +# limitations under the License. |
| 16 | + |
| 17 | +import logging |
| 18 | + |
| 19 | +from .component import CoreSightCoreComponent |
| 20 | +from ..core.target import Target |
| 21 | + |
| 22 | +LOG = logging.getLogger(__name__) |
| 23 | + |
| 24 | +DEAD_VALUE = 0 |
| 25 | + |
| 26 | + |
| 27 | +class GenericMemAPTarget(Target, CoreSightCoreComponent): |
| 28 | + """! @brief This target represents ARM debug Access Port without a CPU |
| 29 | + |
| 30 | + It may be used to access the address space of the target via Access Ports |
| 31 | + without real ARM CPU core behind it. For instance Cypress PSoC64 devices have |
| 32 | + three APs implemented in the hardware: |
| 33 | + * AP #0 -> CPU-less AHB AP |
| 34 | + * AP #1 -> Cortex-M0+ AP |
| 35 | + * AP #2 -> Cortex-M4F AP |
| 36 | + Depending on the protection state, AP #1 and AP #2 can be permanently disabled. |
| 37 | + This class allows to communicate with Secure FW running on the target via AP #0. |
| 38 | + |
| 39 | + Most of the methods in this class (except memory access methods) are empty/dummy. |
| 40 | + """ |
| 41 | + |
| 42 | + def __init__(self, session, ap, memory_map=None, core_num=0, cmpid=None, address=None): |
| 43 | + Target.__init__(self, session, memory_map) |
| 44 | + CoreSightCoreComponent.__init__(self, ap, cmpid, address) |
| 45 | + self.core_number = core_num |
| 46 | + self.core_type = DEAD_VALUE |
| 47 | + self._target_context = None |
| 48 | + self.register_list = [] |
| 49 | + |
| 50 | + def add_child(self, cmp): |
| 51 | + pass |
| 52 | + |
| 53 | + @property |
| 54 | + def supported_security_states(self): |
| 55 | + return Target.SecurityState.NONSECURE, |
| 56 | + |
| 57 | + def init(self): |
| 58 | + pass |
| 59 | + |
| 60 | + def disconnect(self, resume=True): |
| 61 | + pass |
| 62 | + |
| 63 | + def write_memory(self, addr, value, transfer_size=32): |
| 64 | + self.ap.write_memory(addr, value, transfer_size) |
| 65 | + |
| 66 | + def read_memory(self, addr, transfer_size=32, now=True): |
| 67 | + return self.ap.read_memory(addr, transfer_size, True) |
| 68 | + |
| 69 | + def read_memory_block8(self, addr, size): |
| 70 | + return self.ap.read_memory_block8(addr, size) |
| 71 | + |
| 72 | + def write_memory_block8(self, addr, data): |
| 73 | + self.ap.write_memory_block8(addr, data) |
| 74 | + |
| 75 | + def write_memory_block32(self, addr, data): |
| 76 | + self.ap.write_memory_block32(addr, data) |
| 77 | + |
| 78 | + def read_memory_block32(self, addr, size): |
| 79 | + return self.ap.read_memory_block32(addr, size) |
| 80 | + |
| 81 | + def halt(self): |
| 82 | + pass |
| 83 | + |
| 84 | + def step(self, disable_interrupts=True, start=0, end=0): |
| 85 | + pass |
| 86 | + |
| 87 | + def reset(self, reset_type=None): |
| 88 | + pass |
| 89 | + |
| 90 | + def reset_and_halt(self, reset_type=None): |
| 91 | + self.reset(reset_type) |
| 92 | + pass |
| 93 | + |
| 94 | + def get_state(self): |
| 95 | + return Target.State.HALTED |
| 96 | + |
| 97 | + def get_security_state(self): |
| 98 | + return Target.SecurityState.NONSECURE |
| 99 | + |
| 100 | + def is_running(self): |
| 101 | + return self.get_state() == Target.State.RUNNING |
| 102 | + |
| 103 | + def is_halted(self): |
| 104 | + return self.get_state() == Target.State.HALTED |
| 105 | + |
| 106 | + def resume(self): |
| 107 | + pass |
| 108 | + |
| 109 | + def find_breakpoint(self, addr): |
| 110 | + return None |
| 111 | + |
| 112 | + def read_core_register(self, reg): |
| 113 | + return DEAD_VALUE |
| 114 | + |
| 115 | + def read_core_register_raw(self, reg): |
| 116 | + return DEAD_VALUE |
| 117 | + |
| 118 | + def read_core_registers_raw(self, reg_list): |
| 119 | + return [DEAD_VALUE] * len(reg_list) |
| 120 | + |
| 121 | + def write_core_register(self, reg, data): |
| 122 | + pass |
| 123 | + |
| 124 | + def write_core_register_raw(self, reg, data): |
| 125 | + pass |
| 126 | + |
| 127 | + def write_core_registers_raw(self, reg_list, data_list): |
| 128 | + pass |
| 129 | + |
| 130 | + def set_breakpoint(self, addr, type=Target.BreakpointType.AUTO): |
| 131 | + return False |
| 132 | + |
| 133 | + def remove_breakpoint(self, addr): |
| 134 | + pass |
| 135 | + |
| 136 | + def get_breakpoint_type(self, addr): |
| 137 | + return None |
| 138 | + |
| 139 | + def set_watchpoint(self, addr, size, type): |
| 140 | + return False |
| 141 | + |
| 142 | + def remove_watchpoint(self, addr, size, type): |
| 143 | + pass |
| 144 | + |
| 145 | + def set_vector_catch(self, enable_mask): |
| 146 | + pass |
| 147 | + |
| 148 | + def get_vector_catch(self): |
| 149 | + return 0 |
| 150 | + |
| 151 | + def get_target_xml(self): |
| 152 | + return None |
| 153 | + |
| 154 | + def get_halt_reason(self): |
| 155 | + return Target.HaltReason.DEBUG |
| 156 | + |
| 157 | + def get_target_context(self, core=None): |
| 158 | + return self._target_context |
| 159 | + |
| 160 | + def set_target_context(self, context): |
| 161 | + self._target_context = context |
| 162 | + |
| 163 | + def create_init_sequence(self): |
| 164 | + pass |
| 165 | + |
| 166 | + def mass_erase(self): |
| 167 | + pass |
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