SDC Part-2
Welcome to ASIC Alley!!
System Interface constraints:
(commands to make sure that the interface to your P&R block will not cause transition or capacitance violations when connected to external circuitry in a chip)
Design Rule constraints:
Design constraints define the requirements that must be met by the compilation flow for the design to be functional in hardware.
Design constraints:
Design Rule constraints:
These are implicit constraints defined in the library. These are technology-specific restrictions that our design must meet to function as intended. By default, design rule constraints have a higher priority than optimization constraints.
Notes: Can not discard or override these rules. Design rules constraints are associated with the pins of cells from a logic library, and they constrain the nets of a design.
Maximum transition time: set_max_transition (It will be available only for input pin.)
This constraint is based on library data. For the Non linear delay model (NLDM), output transition time is a function of input transition and output load.
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How to calculate: CMOS delay model: transition time = drive R X load C
Non linear delay model : transition time form table lookup and interpolation/ extrapolation.
When we talk about transition time (also called rise time or fall time), we’re referring to how quickly a signal changes from one state to another. If this transition time is too slow, it can lead to timing issues in a digital circuit.
One way to reduce transition time of the nets is by adding a buffer at the output of the driving cell.
Frequency Dependency: For high-frequency designs, a lower max_transition value can help in reducing the overall delay and improving performance (It also varies with frequency of a cell.
Max fanout:
(available for output pins only.)
Maximum fanout of an output measures its load-driving capability.It is the greatest number of input pins of gates to which output can be safely connected.
The maximum fanout constraint (max_fanout) is a design parameter that limits the number of loads (gates or cells) that a single output can drive. By setting this constraint, designers ensure that the driving cell’s output signal remains strong and transitions quickly, preventing issues like signal degradation, timing delays, and excessive power consumption.
How to Calculate Max Fanout:
- Identify the Driving Cell: Determine the cell or gate whose output signal is driving other cells.
- Count the Loads: Identify all the cells or gates that are connected to the output of the driving cell.
- Set the Max Fanout Constraint: Based on design requirements and performance criteria, set a maximum allowable number of loads that the driving cell can handle.
Minimum capacitance:
Lower priority constraints. Lower range of loads which a cell has been characterized to operate. Threshold kind of strategy. If this get violated then I need to fix the sizing of the driver.
Note: The optimization constraints will be covered in next blog so stay tuned!!
