SDC Part 3
Optimization constraints:
They are explicit and set by the designer.they must be realistic and describe the design goals like area and timing. set_max_area, set_min_area are area constraints.
Timing constraints:
Clock specific constraints that affect synthesis and timing analysis.
Wire load models:
wire load models are models of resistive and capacitive loads that exist on the nets or wires interconnecting logic cells. Design compiler uses wire load models to estimate the resistance and capacitance of nets prior to physical layout of the circuit
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set_wire_load wire_load_name -mode mode
Area constraints:
we constrain our design during synthesis, we usually prefer to set_max_area to 0, knowing that the synthesis tool will never get there, but to force the synthesis tool to minimize the die area during synthesis. The set_max_area command in dc_shell accepts area constraints in square miles (thousandths of an inch).
Operating conditions:
Process, voltage, temperature (PVT)
Three factors contribute to how a design compiler optimizes your design — process, voltage and temperature (PVT). These 3 factors together provide minimum and maximum cell and wire delays that, depending on which combination of PVT is chosen for optimization. We specify the operating conditions we want to use with the following design compiler command:
set_operating_conditions -library library_name condition
By default, no operating conditions are applied to a design being synthesized. You may determine which libraries and operating conditions are available by using the following design compiler commands.
list -libraries and report_lib library_name
