Verilog2

1. wire-> continuous assignment, contiuously driven
2. reg-> procedural assignment; stores value
3. What is the use of non-blocking assignment in behavioral modeling of verilog? How is it different from blocking-assignment?The nonblocking statements allow the schedule assignments without blocking the procedural flow. Whereas a blocking statement must be executed before the execution of the statements that follow it in a sequential block. The blocking statements are executed in the same order as they are entered. The nonblocking procedural statement cab be used to make several register assignments within the same time step without regard to order or dependence upon each other. It means that nonblocking statements resemble the actual hardware more than the Blocking assignments.
4. What is the difference between inertial and transport delays? What are the applications?

ans. inertial delay — — — — — →assign #10 out = in1 & in2; execution delay by #10

transport delay — — — — — — -> out <= #10 in; execution at t=0 and then value assigned to it after 10 sec

5. What is the final value of “b” in the following verilog codes?

6. #5 a = b + cThis is called regular delay control. The execution of the statement a = b+c will be delayed by 5ns.a = #5 b + cThis is called intra-assignment delay control. The values of b and c at time=0 are used to calculate b+c and that value will be assigned to ‘a’ after 5ns.

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7. What do x and y specify in the following verilog statement? `timescale x / y

x —-> ref time unit that specifies the unit of measurment for delays and time; y — -> time precision, precision to which the delays are rounded off during simulation.

8. differene between always and intial — — -> 2 strutured procedure statement in verilog.

intial — → starts at t=0 and executes once during a simulation.these blocks is not synthesizable.

always — -> starts at t=0; runs continuously in a loop fashion.This statement is used to model a block of activity that is repeated continuously in a digital circuit. Always block is synthesizable.

9. Explain the following commands of Verilog: case, casex and casez

case 0,1,x,z

casex x and z as dont care

casez z as a dont care

10. if both default and 11 are removed, then latch will be formed. Suppose, if the pattern 11 appears at the input, but as nothing matches to 11 in case alternatives the output will not change. This forms the latch, that is the output holds the previous value. To avoid the latch formation, it is better to use always default statement.