Metastability
Metastability is a fundamental challenge in digital system design, particularly in circuits that involve asynchronous interactions. It arises when a flip-flop samples an input that does not satisfy setup or hold time requirements, causing the circuit to enter an indeterminate state in which the output is neither a valid logical ‘0’ nor ‘1’ for an unpredictable duration. Although metastability is often simplistically described as “randomness” or “uncertainty” between logic levels during data transfer between sequential elements, this description alone is insufficient for understanding the phenomenon or identifying systems that are susceptible to it.
At its core, metastability occurs due to the inherent limitations of flip-flops and latches in resolving conflicting input signals during critical timing windows. When an input transitions near the clock edge, the internal latch stages of the flip-flop may both be partially active, creating a state where internal nodes are at intermediate voltages. This unstable condition can persist for a time that depends on the flip-flop’s characteristics, often described by its resolution time constant. Such behavior is particularly pronounced in circuits where signals cross from one asynchronous clock domain to another, or where multiple latches are cascaded without proper timing alignment. The result of these metastable events can include prolonged indeterminate outputs, propagation of invalid logic levels through downstream sequential elements, corrupted data, and potential timing violations that affect the overall system performance.
Standard Edge-triggerd FF Circuit Diagram And Metastability
A conventional edge-triggered flip-flop can be modeled as a cascade of two level-sensitive latches, each controlled by opposite phases of the clock. In this structure, one latch is transparent during the high phase of the clock, while the other is transparent during the low phase. By selecting which latch is transparent in which phase, the designer determines whether the overall flip-flop is triggered on the rising or falling edge of the clock. The general circuit diagram of a latch is shown below in Figure 1.
A rising-edge–triggered D flip-flop can be constructed by connecting a low-level–transparent D-latch to a high-level–transparent D-latch. When the clock is low, the first latch is transparent and samples the input, while the second latch holds its previous value. At the moment the clock transitions from low to high, the first latch closes and the second latch opens, transferring the stored data to the output. Because the output updates only at this clock transition, the combined circuit behaves as a positive edge–triggered D flip-flop. The general circuit diagram of a FF is shown below in Figure 2.
To observe metastability, the data input must transition within the setup–hold time window of the flip-flop. In this region, the master latch is still resolving its stored value, and the cross-coupled inverters have not yet settled to a stable logic level. An output whose settling time (clock-to-Q delay) exceeds its nominal value can be regarded as evidence of metastability. Although the metastable state produces a non-valid voltage level — neither a logic ‘0’ nor a logic ‘1’ — the circuit will eventually resolve to one of the two stable logic states. An example of such metastable behavior is illustrated in the LTspice waveform shown below in Figure 3 and Figure 4.
Probablity of Metastability
The probability of metastability is influenced by device-level parameters, including the MOSFET transconductance (gm), input capacitance (gc), threshold voltage(Vth), clock frequency(Fc), data transition rate(Fd), and the width of the setup–hold window(Tw). Understanding the impact of these parameters requires a clear comprehension of the circuit’s behavior during a metastable event, when the internal nodes of the latch or flip-flop momentarily fail to resolve to a valid logic level. During this interval, the device characteristics and timing conditions collectively determine both the likelihood of entering metastability and the duration required for the circuit to return to a stable state.
Master D-latch while metastability
When the master D-latch enters a metastable state, its storage element can be approximated by a pair of cross-coupled inverters operating in the saturation region. This small-signal representation captures the behavior of the latch during metastability, as illustrated in Figure 5.
The behavior of this circuit exhibits a capacitive exponential response, as expected from the effective resistance determined by the MOSFET transconductance and the total input capacitance of the devices. This dynamic can be described analytically by the expression given in Equation 1.
As discussed above, the metastable state and its dynamic behavior are governed by the time constant -tau- and the voltage difference between the two internal nodes. These parameters are determined by both the time-varying voltage and the intrinsic device characteristics — specifically, the transconductance and input capacitance of the transistors — which are fixed for a given system. Therefore, the duration and evolution of metastability are influenced by the transistor design as well as the dynamic operating conditions of the circuit. An example simulation of this behavior, implemented in LTspice, along with the corresponding waveform, is presented in Figures 6 and 7.
As illustrated in Figure 7, the settling behavior of Q varies as a result of the difference of voltage between the internal nodes described above. Variations in the rise moment of the data input influence this voltage difference, which in turn affects the settling time, as expected.
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Clock Frequency and Transition Rate while Metastability
Metastability occurs when data changes between setup-hold time window. For asynchronous digital system, the data can change any point of transition. Therefore, the probablity of the change of data between setup-hold time window can be repesented below in equation 2 below.
Moreover, the input data need not transition on every clock cycle. Consequently, the rate of data changes also influences the likelihood of flip-flop failure, i.e., the probability of entering a metastable state. This probability of failure can be expressed as shown in Equation 3.
Failure Rate of Asynchronous Digital System
As stated in the previous sections, the behavior of a metastable state follows an exponential characteristic. Let S denote the time available for the flip-flop to resolve the metastable condition, and let tau represent the intrinsic time constant of the flip-flop. Under these assumptions, the expression can be reformulated as shown in Equation 4.
The unit of this expression corresponds to the expected number of failures in which metastable data propagates after a resolution time S. Consequently, the inverse of this quantity represents the mean time interval between such failures. This relationship is expressed in Equation 5. This expression is called MTBF (Mean Time Between Failure).
Based on the system parameters, the MTBF can be computed accordingly. The resulting MTBF value indicates how frequently the system is expected to experience metastability-induced failures. This metric provides critical insight for the designer in evaluating the reliability and overall stability of the system.
Example:
Tau = 10 ps, Tw = 20ps, Fc= 100MHz, S = Tc*2, Fd = 1/5 (change one each 5 cycles)
MTBF = 3.08×10864 years
Tau = 10 ps, Tw = 20ps, Fc= 100MHz, S = Tc, Fd = 1/5 (change one each 5 cycles)
MTBF = 1.56×10430 years
This is quite long duration to see a failure.
In summary, metastability represents a critical concern in digital system design, particularly when dealing with asynchronous signals or multiple clock domains. Understanding its causes, potential propagation, and system-level impacts is essential for designing reliable circuits. By applying appropriate mitigation strategies — such as synchronizer chains, careful clock-domain crossing design, and rigorous timing constraints — engineers can significantly reduce the likelihood of metastable events, thereby ensuring functional correctness and overall system stability.
R. Ginosar, “Metastability and Synchronizers: A Tutorial,” IEEE Design & Test of Computers, vol. 28, no. 5, pp. 23–35, Sep.–Oct. 2011. doi:10.1109/MDT.2011.113
