FPGA — VERİLOG-LOGİC
Learning fpga basics.
Primarily learning fpga we understand some definitions and operants.
Logic gates, boolean algebra, max-min terms, SOP, POS, karnough map, truth tables, adders, binary aritmethics etc.
1-) Fundamental logic gates are OR gate, AND gate, NOT gate and comes after that other logic gates those are NAND, NOR, XOR XNOR.
logic values maybe get some values on simulation these are 1,0,x,z.
x is undefined or dont care state,
z is high impedans that means wire doest not connet anywhere
logic 1 means high or +5, +3 +1 volt depend on system
logic 0 means low or 0 volt,
2-) gates turth tables, and drawing karnough maps and skect the function of combinatioal circuits.
basic assignments
inputs are A, B, output is Y so
and inst0 (y, A,B) or assign y = A & B ;
or inst1 (y, A,B) or assign y = A | B ;
not inst2 (y, A) or assign y = ~A ;
xor inst3 (y, A,B) or assign y = A ^ B;
xnor inst4 (y, A,B) or assign y = ~(A ^ B);
nor inst5 (y, A,B) or assign y = ~(A | B);
nand inst6 (y, A,B) or assign y = ~(A & B);
structural design or data flow design there no is no much difference.
The other important elements is Multiplexers. FPGA chips are full of mux. Mux are using to select the data which want to connect trough to output wire.
2power N represent that how many inputs are there so N is number the select bits.if there are 2 input and the select bit number is one,,
if there are 4 input and the select bits number is 2
and there are 4–8 inputs and selects bits must be 3 bits, etc. select bit number comes 2 ^N = inputs number.
and assume A and B inputi select bit S and output terminal is Y that the mux’s function = [ (~S & A) | ( S & B ) ]
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Eventually last elements is half and full adder, full adder consist of 2 half adder and 1 or gate. Full adder have 3 inputs and 2 outputs, generally inputs are named as A,B Cin and the outputs are Sum, Carry.
- note that, subtracting with logic circuits uses adders..
simple alu can be design this informations, add sub, xor or and.. modules
https://github.com/neomehmet/verilog-fpga.git
gh repo clone neomehmet/verilog-fpga
3-) Finite State Machines, that method is the heart of sequential designs. there is a problem to solve, first step is sketcing state diagrams then state tables or data path. FSM comes with sequential designs. if the design required past or future data, the registers must using. Registers run with enable and clock signals and registers storage data.
module comb( input inv, input [3:0] data, output reg [3:0] result );
always@(inv , data) // trigger with inv or data doesn’t matter
if( inv ) result <= ~data;
else result <= data;
endmodule
module dfifo(input clk, input [3:0] d, output reg [3:0] q );
always @ ( posedge clk )
begin // simple D fifo
q <= d; // non blocking assignment <= must be in the always block
end
endmodule
//=================//
// behavioural mux //
//====================//
module mux2x1( input lsb, msb, sel output y);
assign y = sel ? msb , lsb;
endmodule
//==================/
//multi bits bus declaration in verilog
//==================//
module myNot(input [3:0] a, output [3:0] y );
not(y[0], a[0] );
not(y[1], a[1] );
not(y[2], a[2] );
not(y[3], a[3] );
endmodule
//===================//
//parameter design with loops “for”//
// Assume module add is adder //
//==================//
module parametricAdd#(parameter N = 4)
(input [N-1:0] a,b, output [N-1:0] y);
genvar i; // generate variable i for loop cycles
generate
for ( i =0; i<N; i = i+1 ) begin
add inst(sum[i], a[i],b[i]); end
endgenerate
endmodule
//=================//
// wierd mux with always //
//================//
module mux3(input a,b,c, sel, output y);
always @ ( a,b,c,sel) begin
case(sel):
2'b00 : y = a;
2'b01 : y = b;
2'b10 : Y = c;
endcase
end
endmodule
from c to verilog with fsm
