Choose the PCB Stack-Up Before You Route the First Critical Net
A buildable stack-up starts with reference planes and ends with an agreement your fabricator can actually follow.
Design Review Notes · 02
“Four layers, 1.6 mm, FR-4” sounds like a stack-up. It is enough to start a quotation. It leaves several decisions unanswered for the engineer about to route a controlled-impedance interface.
Which copper does the signal reference? How far away is it after lamination? What trace width fits between the connector pads? If the fabricator proposes a different construction, which of those answers changes?
The useful time to settle this is while placement can still move. Once a difficult escape is routed, a new impedance width can become a placement problem. The previous note followed return current through the finished layout. This one moves that review ahead of routing.
Give the critical routes a reference before you give them a layer
Start with a short routing plan. List the interfaces whose geometry needs control, the fastest edges worth investigating, and the analog routes that cannot tolerate nearby switching activity. Add the layer on which each route is likely to leave its package and reach its connector. That last detail often exposes a weak stack-up sooner than the overall net count does.
For each proposed routing layer, name the reference plane. Then look at the actual placement: will the route cross a cutout, a plane boundary, or a clearance field? A label reading “GND” in the stack manager does not prove that useful reference copper exists under the route.
Consider a hypothetical controller whose critical signals mostly fit on the outer layers. Ground planes immediately inside those layers can make the return-path plan straightforward. The power distribution and remaining routes still have to fit. If they do not, revisit placement and layer count together; do not turn the reference plane into a routing layer halfway through the job and leave the original review unchanged.
Also mark unavoidable layer changes. When the old and new references are the same ground net, plan a nearby connection between those planes. A change between different reference nets needs a separate AC-return-path analysis. TI distinguishes these cases in its high-speed layout guidance, section 3.5. This is a reason to decide the layer assignment early: the necessary return transition needs physical space.
The output of this step should fit on one page: critical net group, permitted routing layers, reference plane, and transition approach. Treat unknown entries as open design decisions. Do not bury them inside a generic “signal integrity review” task.
Calculate with the local dielectric thickness, not the board thickness
The 1.6 mm dimension describes the complete board. A microstrip impedance calculation needs the distance between that trace and its reference plane. Two boards can have the same finished thickness and very different outer-layer geometries.
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Suppose two candidate constructions place the top ground reference 0.10 mm and 0.30 mm below the signal, respectively. Those are illustrative dimensions, not recommended builds. Keeping the trace width unchanged does not preserve the same impedance. In a simple microstrip comparison with the other parameters held fixed, increasing that separation raises characteristic impedance. Recalculate before approving the substitution.
Use the fabricator’s proposed pressed dielectric thicknesses and material construction. Record the dielectric constant used by the model and the frequency or method associated with it. For outer layers, check the solder-mask assumptions. For differential pairs, include the pair gap as well as trace width. Altium’s controlled-impedance documentation describes how geometry and surrounding materials enter the calculation.
Be precise about copper, too. Starting foil and finished conductor thickness are different quantities. Plating and etching affect the result; Eurocircuits explains that distinction for inner and outer layers. “One ounce” alone is an incomplete handoff between a calculation and a manufacturing process.
Now test whether the calculated geometry is routable. Can the pair leave the component pads without an excessive neck-down? Can the required gap survive the connector escape? Where it cannot, identify the short exception and decide what analysis it needs. A nominal impedance result in a calculator does not clear a discontinuity in the layout.
I would keep the initial calculation beside the fabricator’s proposed geometry and reconcile differences before routing. Ask which material, mask or conductor assumptions account for the discrepancy. Averaging two answers gives you a third answer with no defined physical construction behind it.
Release an agreed construction, including how changes are approved
A useful stack-up review ends with a document somebody else can build from. Ask for the proposed production construction early, with its revision identifier. Standard available builds are worth evaluating before specifying an unusual dielectric combination. Eurocircuits’ buildup editor guide, for example, makes material and construction choices explicit within the selected manufacturing service.
Put these items in the release package:
- Construction: layer order, reference nets, material identification, pressed dielectric thicknesses, finished copper, overall thickness and applicable tolerances.
- Impedance requirements: net class, signal layer, reference layer or layers, target and tolerance, trace width, and pair gap where relevant.
- Change control: which dimensions may be adjusted, who approves a proposed substitution, and which CAD rules must be updated before fabrication.
- Verification: the required coupon structures, measurement report and traceability to the build, agreed with the supplier.
A coupon gives evidence about the manufactured test structure. It does not exercise your connector launch, every via or the receiver. Keep that distinction in the acceptance plan. As a concrete manufacturing example, Gatema’s impedance-control sheet requests signal and reference layers, impedance targets and tolerances, and describes measurements on a coupon included in the production panel.
For a broader layer-planning reference, PCBSync’s stack-up guide sits alongside this review. The project-specific deliverable remains the agreed construction and the routing rules derived from it.
Before releasing the first critical route, have another engineer explain its reference, its geometry and the proposed build revision from the same set of files. If those answers disagree, resolve the document mismatch now. It is much easier while the route is still a plan.
Next: a decoupling capacitor can be close to the IC while its current loop is still too large.
