How SRAM works internally : a simple breakdown

if you have ever wondered how your computer remembers things super fast, even faster than the RAM sitting next to your CPU, the answer is something called sram, or static ram. in this post i want to break down how a single sram memory cell actually works, starting from the most basic building block, the mosfet, all the way up to how it reads and writes a single bit of data.

Let’s start small, with transistors

before we can understand sram, we need to understand mosfets, because that is literally what sram is built out of. there are two types of mosfets that matter here, nmos and pmos, and the easiest way to think about them is as switches.

Fig. The symbol of (a) a PMOS transistor and (b) an NMOS transistor

an nmos transistor turns on when you give it a 1 at its gate. give it a 0 and it turns off. think of it like a light switch that only responds to “high” signals.

a pmos transistor is the exact opposite. give it a 0 at the gate and it acts like a wire, letting current flow through. give it a 1 and it switches off.

so nmos likes 1, pmos likes 0. simple as that.

Building an inverter (not gate)

Fig. CMOS Logic Gate

once you combine one nmos and one pmos together, you get what is called an inverter, or a not gate. it does exactly what the name says, it flips whatever you put in.

• give it a 0, and the output becomes 1
• give it a 1, and the output becomes 0

this little inverter is the heart of everything that comes next.

The sram cell: six transistors, one bit

now here is the interesting part. to actually store one single bit of memory, sram uses six transistors. that’s why you’ll often hear it called a “6T SRAM cell.”

Fig. Standard 6T-SRAM cell circuit

the six transistors are basically two inverters connected back to back, plus two extra “access” transistors that control when we are allowed to read or write. looking at the actual circuit, here’s how they’re labeled:

• M2 and M4 are the two pmos transistors, sitting up top, connected to VDD
• M1 and M3 are the two nmos transistors, sitting at the bottom, connected to ground
• M2 + M1 form the first inverter, and its output is Q_bar
• M4 + M3 form the second inverter, and its output is Q
• M5 and M6 are the access transistors. M5 sits between BL_bar and the Q_bar node, and M6 sits between BL and the Q node. both of their gates are tied to WL

so the two inverters are cross coupled, meaning Q feeds into the M2/M1 inverter, and Q_bar feeds into the M4/M3 inverter, and each one’s output becomes the other one’s input. that loop is what locks the value in place.

a few important terms before we go further:

• WL (wordline) — this line controls whether we are allowed to read from or write to the cell. think of it as the “permission” signal.
• BL / BL_bar (bitline and bitline bar) — these are the lines we use to actually sense what value is stored, or to push a new value into the cell when writing.
• Q / Q_bar — these are the outputs of the two cross connected inverters. Q feeds into one inverter, and that inverter’s output feeds back as the input to the other one, and vice versa. this back and forth loop is what actually “holds” the bit in place.

because the two inverters feed into each other, whatever value is sitting there stays locked in, as long as power is supplied. that’s basically the “hold” state, and it’s the default state of the cell when nothing else is happening.

The three states of an sram cell

an sram cell can be in one of three states at any point:

1. hold — just sitting there, keeping its value, doing nothing
2. read — we want to check what value is stored
3. write — we want to change the value that’s stored

let’s walk through read and write in detail, since that’s where the real magic happens.

How a read operation works

let’s say the cell currently holds Q = 1 and Q_bar = 0. before we even try to read anything, both BL and BL_bar are precharged, meaning CB and CB_bar, the parasitic capacitance sitting on those lines, are charged up to VDD (high voltage) ahead of time. this precharging step matters a lot for what happens next.

Fig. SRAM bit cell holding Q = 1 & Q_bar = 0

now, because Q = 1 and Q_bar = 0, this turns M1 and M4 on, and turns M2 and M3 off. this is basically the internal state of the cell reacting to what’s already stored inside it, and it’s exactly what keeps the loop stable while nothing else is happening.

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next, we set WL = 1, which is our signal saying “okay, we want to access this cell now.” this turns on M5 and M6, the two access transistors that connect the cell to the bitlines.

here’s the clever part. on the M6 side (the Q side, connected to BL), there is no potential difference, since Q is already sitting at VDD and CB was just charged to VDD too, so BL stays at its precharged level and doesn’t discharge at all. on the M5 side (the Q_bar side, connected to BL_bar), there is a potential difference, since Q_bar is 0 but CB_bar was precharged high, so a small voltage change (we call it delta v) happens as CB_bar starts to discharge slightly through M5 and M1, pulling BL_bar down with it.

so now we have a tiny voltage gap between BL and BL_bar. that’s not much to work with, so we bring in a sense amplifier, whose whole job is to detect and amplify this small difference:

• if BL ends up higher than BL_bar, it reads the value as 1
• if BL ends up lower than BL_bar, it reads the value as 0

that’s the whole read operation. it’s really just detecting a tiny voltage imbalance and blowing it up into a clean digital 1 or 0.

CB/CB_bar aren’t real capacitors. they’re the parasitic capacitance of the bitline wire itself, drawn in because it’s what makes the read voltage swing so small.

How a write operation works

writing is basically the opposite process, but instead of sensing a value, we are forcing one in.

Fig. SRAM bit cell holding Q = 0 & Q_bar = 1

let’s say the cell currently has 0 stored, and we want to write a 1 into it.

first, WL = 1 again, turning on M5 and M6, the access transistors, so we can talk to the cell.

then, we force the values we want onto the bitlines directly, so BL = 1 and BL_bar = 0, since we’re writing a 1.

because we are pushing BL_bar = 0 directly into the cell through M5, it essentially grounds Q_bar. as the voltage at Q_bar drops below the threshold voltage of the M4/M3 inverter, that inverter switches off, breaking the old feedback loop that was holding the previous value.

once that happens, M4 turns on, and Q gets pulled up to VDD, meaning it’s now storing a 1, exactly what we wanted.

writing a 0 works the exact same way, just reversed: you’d set BL= 0 and BL_bar = 1 instead, and the cell would end up storing 0.

why this design works so well

the reason sram is so fast is because of this cross-coupled inverter design. once a value is written, it just sits there in a stable feedback loop, no need to constantly refresh it like DRAM does. the tradeoff is that it takes six transistors per bit instead of just one (like DRAM uses), so sram takes up more physical space on a chip and costs more. that’s exactly why sram is used in small, fast places like cpu caches, while dram is used for your main system memory where you need a lot more capacity.

so next time your cpu accesses something from its cache in a fraction of a nanosecond, you’ll know there’s a tiny six transistor circuit somewhere on that chip, quietly holding a single bit steady, ready to be read or rewritten in an instant.