Half Adder
Introduction
Half adder is a combinational circuit that performs an arithmetic addition of two bits. Half adder takes two inputs and produces two outputs. Let x, y be the two inputs, and S ( sum ), C ( carry ) be the two outputs.
Why we need two outputs?
This is because if we add ‘1’ and ‘1’ then the result is a 2-bit number. Therefore, we need two bits to represent the sum. S ( sum ) is used to represent the least significant bit and C ( carry ) is used to represent the most significant bit.
- 0 + 0 = 00
- 0 + 1 = 01
- 1 + 0 = 01
- 1 + 1 = 10
Truth Table
K-map
Implementation of Half-adder
Half adder using AND, OR, NOT gate
Half adder using XOR and AND gate
Half adder using NAND gate
Get ButtWait!’s stories in your inbox
Join Medium for free to get updates from this writer.
The minimum number of NAND gates required to design a half-adder is 5.
Half adder using NOR gate
The minimum number of NOR gates required to design a half-adder is 5.
Half adder using 2×1 Multiplexer
We need two 2×1 multiplexers to implement a half-adder. One for sum bit and one for carry bit.
Half adder using 2 to 4 Decoder
Note
The term “Half-Adder” stems from the fact that two half-adders can be used to implement a full-adder.
Read Next
