ARM Thumb Instruction Encoding Explained

image credit-The ARM Thumb®-2 Core Technology Architecture Extensions — ppt download

1. ARM Based Encoding

ARM provided a RISC-based processor architecture design, and as with any such architecture, defining the instruction set used by the target processor was a key aspect in achieving an optimal and efficient design — both at the hardware and software levels.

Initially, ARM used a basic 32-bit instruction format, where each instruction performed a simple operation. As a result, ARM designs featured separate memory access instructions like load and store and basic arithmetic instructions such as add/subs/mul/div ... . This approach was intended to align with the core RISC principle of executing each instruction in a single clock cycle.

ARM has already deployed 32-bit instruction encoding, commonly referred to as ARM instruction encoding, in their processor architectures such as ARMv1, ARMv2 and ARMv3.

Although encoding instructions as 32 bits helped embed operands within the instructions themselves, it also led to a significant increase in code size. For risc based processors, limited program memory was common, so there has always been a space-time tradeoff when using 32-bit instructions in microcontroller chips.

2. Thumb-1 Based Encoding

Thumb instruction encoding was introduced with the ARMv4T architecture. Any ARM version before ARMv4T supports only the ARM instruction encoding.

ARMv4T featured a mix of 32-bit ARM instruction encoding and 16-bit Thumb instruction encoding. The main goal was to improve code density with the new 16-bit instructions, serving more as a complement to the existing 32-bit ARM instructions rather than a full substitute.

Get Wadix Technologies’s stories in your inbox

Join Medium for free to get updates from this writer.

Remember me for faster sign in

From an execution point of view, each instruction type had its own execution context or state. On ARMv4T , there were two execution states:ARM and THUMB state , each corresponding to the type of instruction being executed. The instruction used to switch between these states was the BX branch with exchange instriction:

• When branching to a target address with 16-bit Thumb instructions, the target address used with BX must have its least significant bit (bit[0]) set to 1.
  For example,

bx 0x00000001

branches to the Thumb state at address 0x00000000 (bit 0 is ignored for the actual jump address).

• When branching to a target address with 32-bit ARM instructions, the target address used with BX must have bit[0] cleared (set to 0).
  For example,

bx 0x00000004

branches to the ARM state at address 0x00000004.

Thumb instruction encoding definitely helped improve code density but also had significant performance limitations. Embedding different instruction operands within the same 16-bit instruction was constrained, which often required breaking down a single operation into multiple 16-bit instructions or switching back and forth between ARM and THUMB states to compensate for Thumb’s performance limitations. However, branching itself introduced overhead, especially on processors without branch prediction units.

The original Thumb instructions — also known as Thumb-1 — could only target a limited number of CPU registers due to their restricted instruction size, which limited the registers that could be directly addressed. As a result, it was often necessary to invoke ARM instructions to access CPU registers in the higher register bank.

3. THUMB-2 Based Encoding

Starting with ARMv6T2, ARM deployed the THUMB-2 instruction encoding, which was then widely adopted in ARMv7 based architetcure designs.

• Thumb-2 supports both 16-bit and 32-bit instruction sizes.
• The 16-bit instructions in Thumb-2 offer significantly higher capability compared to the earlier 16-bit instructions in THUMB-1 , starting to approach the full functionality of the ARM instruction set.
• Better performance and greater flexibility.
• single execution state is used whether the CPU is executing THUMBor ARM instructions — the instruction execution state is always maintained as Thumb.

ARM vs Thumb-1 Vs Thumb-2 time-space benchmarking

If you enjoyed this article, please make sure to Subscribe, Clap, Comment and Check out our online courses today!