BRUNDA RAJ G K·2d agoLatch or Flip-Flop? Identify the Hardware from the RTLOne of the most useful RTL debugging skills is being able to look at a short piece of Verilog and predict what hardware will actually be…
BRUNDA RAJ G K·2d agoClock Divider vs Clock Enable: Why Does the Output Change at a Different Time?A clock divider and a clock enable can both make a circuit appear to operate more slowly.
BRUNDA RAJ G K·4d agoDay 38: Pulse Generators: What If a New Trigger Arrives Before the Old Pulse Ends?While working with edge detection, I started thinking about the next practical question:
BRUNDA RAJ G K·4d agoDay 37: Edge Detection — Why Did My Circuit Count One Event Twice?While working with sequential RTL, I came across an interesting problem:
BRUNDA RAJ G K·6d agoDay 36: Shift Registers — Why Does the Bit Order Look Reversed?While working with sequential RTL, I came across a simple-looking circuit that can easily cause confusion: the shift register.
