Prachi Manglik·Oct 3, 2024Understanding Configuration Objects and Sequence Items in UVM: A Comprehensive GuideIn UVM (Universal Verification Methodology), configuration objects and sequence items are two critical constructs that help in creating…A response icon1
Radha Kulkarni·Nov 6, 2023Step-by-step guide on how to design and implement Counters with testbench code on Xilinx Vivado…In this project, we explore how to implement counters with testbench code using Xilinx Vivado. We cover three types of counters: Up…
Radha Kulkarni·Nov 3, 2023Step-by-step guide on how to design and implement a Half Adder using Testbench code with Xilinx…A Half Adder is a combinational logic circuit that adds two inputs to produce two outputs, Sum and Carry. In my project, I explained the…
Radha Kulkarni·Nov 2, 2023Step-by-step guide on how to design and implement Logic Gates with testbench code on Xilinx Vivado…In this project, I demonstrated how to implement various logic gates using Verilog and Testbench code in Xilinx Vivado.
Mohan Sardar·Oct 20, 2023Synchronous FIFO Design and Verification with SystemVerilog Testbench.This project focuses on the design and verification of a Synchronous FIFO module in Verilog, ensuring synchronized data transfer and…A response icon1
