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Labb3 överkurs 2

miyago
Dec 6th, 2017
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  1. LIBRARY IEEE;
  2. USE ieee.std_logic_1164.ALL;
  3. USE ieee.std_logic_arith.ALL;
  4.  
  5. ENTITY control IS
  6.     PORT ( Start, Clock: IN std_logic;
  7.     Ready: OUT std_logic;
  8.     Lamp: OUT std_logic);
  9. END ENTITY control;
  10.  
  11. ARCHITECTURE counter OF control IS
  12.    
  13.     SUBTYPE tillstand IS integer RANGE 0 TO 19;
  14.     SIGNAL nuvarande: tillstand;
  15.     BEGIN
  16.         Raknare: PROCESS(clock, nuvarande, start)
  17.             BEGIN
  18.  
  19.             IF rising_edge(clock) THEN
  20.                 Ready <= '0';
  21.                 IF (nuvarande = 0 AND start = '1') THEN
  22.                     nuvarande <= 1;
  23.                 ELSIF nuvarande = 19 THEN
  24.                     nuvarande <= 0;
  25.                     Ready <= '1';
  26.                 ELSIF nuvarande > 0 THEN
  27.                     nuvarande <= nuvarande + 1;
  28.                 END IF;
  29.             END IF;
  30.         END PROCESS;
  31.  
  32.  
  33.  
  34.     Lampa: PROCESS(nuvarande)
  35.         BEGIN
  36.             Lamp <= '0';
  37.             IF nuvarande = 0 THEN
  38.                 Lamp <= '0';
  39.             ELSIF nuvarande > 0 THEN
  40.                 Lamp <= '1';
  41.             END IF;
  42.     END PROCESS;
  43. END ARCHITECTURE counter;
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