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- -- Declaramos librerías
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- -- Definimos la entidad del sumador
- entity sumador is
- Port (
- A0, A1, A2, A3: in std_logic; -- Entradas A
- B0, B1, B2, B3: in std_logic; -- Entradas B
- Cin: in std_logic; -- Carry de entrada
- Cout: out std_logic; -- Carry de salida
- S0, S1, S2, S3: out std_logic -- Salidas
- );
- end sumador;
- -- Definimos la arquitectura del sumador
- architecture behavioral of sumador is
- signal A: std_logic_vector(3 downto 0); -- Vector A
- signal B: std_logic_vector(3 downto 0); -- Vector B
- signal S: std_logic_vector(4 downto 0); -- Vector S con Cout
- signal suma: integer;
- begin
- -- Cargamos el vector A.
- process(A3, A2, A1, A0)
- begin
- A(3) <= A3;
- A(2) <= A2;
- A(1) <= A1;
- A(0) <= A0;
- end process;
- -- Cargamos el vector B.
- process(B3, B2, B1, B0)
- begin
- B(3) <= B3;
- B(2) <= B2;
- B(1) <= B1;
- B(0) <= B0;
- end process;
- suma <= conv_integer(A) + conv_integer(B) + conv_integer(Cin);
- S <= conv_std_logic_vector(suma, 5);
- S0 <= S(0);
- S1 <= S(1);
- S2 <= S(2);
- S3 <= S(3);
- Cout <= S(4);
- end behavioral;
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