Resource conflicts in structural hazards occur when multiple instructions in a pipelined processor require access to the same hardware resource at the same time, but the hardware cannot support their simultaneous use.
- Structural hazards reduce the performance of the pipeline by forcing stalls and lowering instruction throughput
- Understanding resource conflicts helps us design better hardware and avoid unnecessary delays.
Try to use one hardware unit at the same time, but only one copy of that unit exists.
Causes of Resource Conflicts
Resource conflicts primarily arise in pipelined architectures due to:
- Insufficient hardware resources (e.g., only one ALU or shared memory for instruction and data access)
- Overlapping execution stages, where different stages of multiple instructions compete for the same resource in the same clock cycle.
A common example is when one instruction is being fetched while another is accessing data memory, but if both share a single memory unit, one must wait—leading to a structural hazard.
Example: Memory Conflict
If the processor uses a single memory unit, the following conflict occurs:
- Instruction in IF stage → needs memory for instruction fetch
- Instruction in MEM stage → needs memory for data read/write
Since there is only one memory, both cannot happen together → structural hazard.
Effects of Resource Conflicts
Resource conflicts cause:
- Pipeline stalls (bubbles)
- Reduced throughput
- Lower instruction-per-cycle (IPC)
- Increased execution time
The processor must either wait or reorder operations to avoid crashes.