Translation Lookaside Buffer (TLB) in Paging

Operating systems use paging to map virtual addresses to physical addresses efficiently. Each process maintains its own Page Table, which contains Page Table Entries (PTEs) responsible for translating virtual page numbers into physical frame numbers. This mechanism enables flexible memory allocation and prevents processes from interfering with each other’s memory space.

• Paging divides memory into fixed-size pages and frames.
• Each process has a separate Page Table for address translation.
• Page Table Entries (PTEs) store the frame number and status bits.
• Paging improves memory protection, isolation, and efficient utilization.

Now the question is where to place the page table, such that overall access time (or reference time) will be less. 

The Problem of Access Time in Paging

When the CPU generates a virtual address, it must be translated into a physical address to access data in main memory. The naive approach stores the entire page table in main memory. Therefore, for every memory access, the following two memory accesses are required:

1. Access the page table in main memory to get the frame number.
2. Access the actual data in the main memory frame.

Note: This leads to a performance problem, as every memory access now requires two memory accesses, causing a significant slowdown.

Why Not Store Page Table in Registers?

Initially, it seemed ideal to store the page table in the high-speed CPU registers to speed up lookups since registers provide the fastest access time. However:

• Registers are very limited in size and can store only a small number of entries.
• For large processes, the page table can be very large. For example, in a 32-bit system with 4 KB page size, the page table may contain around 1 million entries.

Therefore, this approach is impractical and the entire page table is kept in main memory instead.

• To find the frame number: The CPU first accesses the page table in main memory to obtain the frame number similar to the page number.
• To go to the address specified by the frame number: After getting the frame number, the CPU accesses the actual memory location (frame) to read/write the data.

How Does the TLB Work?

When the CPU generates a virtual address, it first looks up the page number in the TLB.

• TLB Hit: It is the situation when, the page number is found in the TLB, the corresponding frame number is retrieved instantly.
• TLB Miss: It is the situation when, the page number is not found in the TLB, the CPU accesses the page table in main memory.

Step-by-Step Process

Steps in TLB Hit:

1. CPU generates a virtual (logical) address. 
2. It is checked in TLB (present). 
3. The corresponding frame number is retrieved, which now tells where the main memory page lies. 

Steps in TLB miss:

1. CPU generates a virtual (logical) address. 
2. It is checked in TLB (not present). 
3. Now the page number is matched to the page table residing in the main memory (assuming the page table contains all PTE). 
4. The corresponding frame number is retrieved, which now tells where the main memory page lies. 
5. The TLB is updated with new PTE (if space is not there, one of the replacement techniques comes into the picture i.e either FIFO, LRU or MFU etc).

Effective memory access time(EMAT)

TLB is used to reduce adequate memory access time as it is a high-speed associative cache. 

EMAT = h(c + m) + (1 - h)(c + 2m)

where:

• h = Hit ratio of the TLB
• m = Main memory access time
• c = TLB access time

Note: A higher hit ratio h significantly reduces EMAT, making the system efficient.

Benefits of Using TLB in Paging

• Faster Address Translation: Reduces the need for repeated page table accesses.
• Better Performance: Reduces average memory access time dramatically.
• Efficient Memory Utilization: Only the most frequently used PTEs are cached in the small, fast TLB.
• Scalability: Especially useful for large address spaces in 64-bit architectures.

Note: Without the TLB, every memory access would require multiple memory lookups, severely degrading performance.