Question 1
In the following truth table, V = 1 if and only if the input is valid.
What function does the truth table represent?
Priority encoder
Decoder
Multiplexer
Demultiplexer
Question 2
Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is
Θ(1)
Θ(Log (n))
Θ(√ n)
Θ(n)
Question 3
Consider a 4-to-1 multiplexer with two select lines S1 and S0, given below
The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is
P\'Q + QR\' + PQ\'R
P\'Q + P\'QR\' + PQR\' + PQ\'R
P\'QR + P\'QR\' + QR\' + PQ\'R
PQR\'
Question 4

Consider the circuit above. Which one of the following options correctly represents f (x, y, z)?
xz' + xy + y'z
xz' + xy + (yz)'
xz + xy + (yz)'
xz + xy' + (yz)'
Question 5
The switching expression corresponding to f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12) is
BC'D' + A'C'D + AB'D
ABC' + ACD + B'C'D
ACD' + A'BC' + AC'D'
A'BD + ACD' + BCD'
Question 6
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
Q = 0, Q' = 1
Q = 1, Q' = 0
Q = 1, Q' = 1
Indeterminate states
Question 7
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?
2
3
4
5
Question 8
Which are the essential prime implicants of the following Boolean function? f(a, b, c) = a'c + ac' + b'c
a'c and ac'
a'c and b'c
a'c only
ac' and bc'
Question 9
Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2-variable Boolean function f = T + R, without using any additional hardware ?
R to X, 1 to Y, T to Z
T to X, R to Y, T to Z
T to X, R to Y, 0 to Z
R to X, 0 to Y, T to Z
Question 10
Consider the following multiplexor where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00, 01, 10, 11 respectively and f is "the output of the multiplexor. EN is the enable input.

The function f(x, y, z) implemented by the above circuit is :
xyz'
xy + z
x + z
None of these
There are 19 questions to complete.