Computer Organization and Architecture GATE CS PYQs

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Question 1

Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O?

  • I/O protection is ensured by operating system routine (s)

  • I/O protection is ensured by a hardware trap

  • I/O protection is ensured during system configuration

  • I/O protection is not possible

Question 2

The amount of ROM needed to implement a 4 bit multiplier is

  • 64 bits

  • 128 bits

  • 1 Kbits

  • 2 Kbits

Question 3

The decimal value 0.5 in IEEE single precision floating point representation has

  • fraction bits of 000…000 and exponent value of 0

  • fraction bits of 000…000 and exponent value of −1

  • fraction bits of 100…000 and exponent value of 0

  • no exact representation

Question 4

A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is

  • 11

  • 14

  • 16

  • 27

Question 5

Register renaming is done in pipelined processors

  • as an alternative to register allocation at compile time

  • for efficient access to function parameters and local variables

  • to handle certain kinds of hazards

  • as part of address translation

Question 6

Consider the data given in previous question. The size of the cache tag directory is

  • 160 Kbits

  • 136 bits

  • 40 Kbits

  • 32 bits

Question 7

The following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which of the following is the correct order in the which the events above occur?

  • QPTRS

  • PTRSQ

  • TRPQS

  • QTPRS

Question 8

Consider two processors P1 and P2 executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P2 takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on P1. If the clock frequency of P1 is 1GHz, then the clock frequency of P2 (in GHz) is _________.

  • 1.6

  • 3.2

  • 1.2

  • 0.8

Question 9

Consider a computer system with a byte-addressable primary memory of size 232 bytes. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB = 210 bytes), and each cache block is of size 64 bytes.

The size of the tag field is __________ bits.

  • 17

  • 18

  • 15

  • 9

Question 10

Consider a computer system with 40-bit virtual addressing and page size of sixteen kilobytes. If the computer system has a one-level page table per process and each page table entry requires 48 bits, then the size of the per-process page table is _________megabytes.   Note : This question was asked as Numerical Answer Type.

  • 384

  • 48

  • 192

  • 96

There are 199 questions to complete.

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