Code Generation Code Generation: Chapter 8
Code Generation Code Generation: Chapter 8
Code Generation
Chapter 8
Chapter 8: Code Generation CS5810 Spring 2009 1
Code Generation
Code Generation
• Severe requirements
– Target program preserve the semantics
– Effective use of available resources
Effective use of available resources
– Itself must be efficient
• Primary tasks
– Instruction selection
I t ti l ti
– Register allocation and assignment
– Instruction ordering
Chapter 8: Code Generation CS5810 Spring 2009 2
Input to the Code Generator
Input to the Code Generator
• IR produced by the front end
IR produced by the front end
– Three address code: quadruples, triples
– Virtual machine: bytecodes, stack‐machine code
Virtual machine: bytecodes stack machine code
– Linear representations: postfix notation
– Graphical representations: DAG, syntax tree
G hi l t ti DAG t t
• Symbol table
– Determine the run‐time addresses of the names in
IR
Chapter 8: Code Generation CS5810 Spring 2009 3
The Target Program
The Target Program
• RISC (reduced instruction set computer)
SC ( educed st uct o set co pute )
– Many registers, three‐address instructions, simple
addressing modes, simple instruction set arch
• CISC (complex instruction set computer)
– few registers, two‐address instructions, various
addressing modes variable length instruction set
addressing modes, variable‐length instruction set
• Stack‐based Machine
– Pushing
Pushing operands onto a stack
operands onto a stack
– Almost disappeared, then revived with Java Virtual
Machine (JVM)
Chapter 8: Code Generation CS5810 Spring 2009 4
The Target Program
The Target Program
• Absolute machine
Absolute machine‐language
language programs
programs
– Can be placed in a fixed location in memory and
immediately executed
• Relocatable machine‐language programs
– Subprograms can be complied separately, then
linked together and loaded for execution by
linking loader
• Assembly‐language program
A bl l
– Code generation easier, need assembly step
Chapter 8: Code Generation CS5810 Spring 2009 5
Instruction Selection
Instruction Selection
• Map the IR into a code sequence that can be
Map the IR into a code sequence that can be
executed by the target machine
x=y+z
x = y + z a = b + c; d = a + e
a = b + c; d = a + e
LD R0, b
,
ADD R0, R0, c
LD R0, y
,
ST a, R0
ADD R0 R0
ADD R0, R0, z
LD R0, a
ST x, R0
ADD R0, R0, e
, ,
ST d, R0
Chapter 8: Code Generation CS5810 Spring 2009 6
Register Allocation
Register Allocation
• Register allocation: select the set of vars
g that will
reside in registers
• Register assignment: pick the specific register
that a var will
that a var reside in
will reside in
t = a + b LL R1, a
R1 a
t = t * c A R1, b
t = t / d M R0 c
M R0, c
D R0, d
ST R1 t
ST R1, t
Chapter 8: Code Generation CS5810 Spring 2009 7
Evaluation Order
Evaluation Order
• The order can affect the efficiency
The order can affect the efficiency
– Some orders require fewer registers
– Picking best order is NP‐complete
Picking best order is NP complete
Chapter 8: Code Generation CS5810 Spring 2009 8
The Target Language
The Target Language
• Assume following kinds of instructions
Assume following kinds of instructions
– Load: LD dst, addr (LD r, x)
– Store: ST x, r
Store: ST x r
– Computation: OP dst, src1, src2 (unary operators
do not have src2)
do not have src2)
– Unconditional jumps: BR L
– Conditional jumps: Bcond
Conditional jumps: Bcond r, L (BLTZ r, L)
r L (BLTZ r L)
Chapter 8: Code Generation CS5810 Spring 2009 9
The Target Language
The Target Language
• Addressing mode
dd ess g ode
– Variable name x
– Indexed address a(r)
• LD R1, a(R2) is R1 = contents(a+contents(R2))
– An integer indexed by a register
• LD R1, 100(R2) is R1 = contents(100+contents(R2))
LD R1 100(R2) is R1 = contents(100+contents(R2))
– Indirect addressing modes
• LD R1, *100(R2) is R1=contents(contents(100+contents(R2))
– Immediate constant address mode
• LD R1, #100
Chapter 8: Code Generation CS5810 Spring 2009 10
The Target Language Example
The Target Language Example
x=y‐z b=a[i]
LD R1, y LD R1, i
LD R2, z
, MUL R1, R1, 8
, ,
SUB R1, R1, R2 LD R2, a(R1)
,
ST x, R1 ,
ST b, R2
x=*p if x < y goto L
LD R1, x
LD R1, p
LD R2, y
LD R2 0(R1)
LD R2, 0(R1)
SUB R1, R1, R2
ST x, R2 Chapter 6: Intermediate Code
Chapter 8: Code Generation
BLTZ R1, L
CS5810 Spring 2009
Generation
11
Program and Instruction Costs
Program and Instruction Costs
• Determining
Determining the actual cost of compiling and
the actual cost of compiling and
running a program is complex
– Cost of an instruction is one plus the costs
Cost of an instruction is one plus the costs
associated with the addressing modes
• LD R0, R1: cost 1
LD R0, R1: cost 1
• LD R0, M: cost 2
• LD R1, *100(R2): cost 3
Chapter 8: Code Generation CS5810 Spring 2009 12
TEST YOURSELF #1
TEST YOURSELF #1
• Generate
Generate code for the following three address
code for the following three address
sequences
x = a[i] y = *q
y = b[i] q = q + 4
Z = x * y *p = y
p = p + 4
Chapter 8: Code Generation CS5810 Spring 2009 13
Basic Blocks and Flow Graphs
Basic Blocks and Flow Graphs
• Partition IR into basic blocks, which are maximal
a tto to bas c b oc s, c ae a a
sequences of consecutive three‐address
instructions that
– The flow of control can only enter the basic block
through the first instruction
– Control leave the block without halting/branching,
Control leave the block without halting/branching
except at the last instruction
• The basic blocks become the nodes of a flow
graph, whose edges indicate which blocks can
follow which other blocks
Chapter 8: Code Generation CS5810 Spring 2009 14
Create Basic Blocks
Create Basic Blocks
• An instruction is a leader if
An instruction is a leader if
– The first instruction in the IR
– The target of a jump
The target of a jump
– Immediately follows a jump
• FFor each leader, its basic block consists of
h l d it b i bl k it f
itself and all the instructions upto (but not
i l di ) th
including) the next leader, or the end of the IR
tl d th d f th IR
Chapter 8: Code Generation CS5810 Spring 2009 15
TEST YOURSELF #2
TEST YOURSELF #2
1) i=1
2) J = 1
• Construct
Construct basic blocks
basic blocks 3) T1 = 10 * I
of the following IR 4) T2 = t1 + j
5) T3 = 8 * t2
6) T4 t3 88
T4 = t3 –
7) A[t4] = 0.0
for i from 1 to 10 do 8) J = j+ 1
for j from 1 to 10 do
for j from 1 to 10 do 9) If j<=10 goto (3)
If j<=10 goto
10) I = I + 1
a[i,j]=0.0 11) If I <= 10 goto (2)
for i from 1 to 10 do
for i from 1 to 10 do 12))
13)
I = 1
T5 = I – 1
a[i,i]=1.0 14) T 6 = 88 * t5
15) A[t6] = 1.0
16) I = i+1
17) I i<= 10 goto (13)
Chapter 8: Code Generation CS5810 Spring 2009 16
Next‐Use
Next Use Information
Information
• Knowing
Knowing when the value of a var
when the value of a var will be used
will be used
next is essential for good code generation
• j uses the value of x computed at i
j uses the value of x computed at i if
– statement i assigns to x
– If j has x as an operand, and control can reach j
If j h d d l hj
from i without an intervening assignment to x
Chapter 8: Code Generation CS5810 Spring 2009 17
Next‐Use
Next Use Algorithm
Algorithm
• Input: a basic block B
Input: a basic block B
• Output: attach to i: x=y+z the next‐use info
• Method: start at the last statement B
Method: start at the last statement B
– Attach to i the information currently found in
symbol table
symbol table
– set x to “not live” and “no next use”
– Set y/z to “live” and the next uses of y/z to I
y/ y/
– Note the steps of 2 and 3 may not be
interchanged
Chapter 8: Code Generation CS5810 Spring 2009 18
Optimization of Basic Blocks
Optimization of Basic Blocks
• Substa
Substantial improvement can be gained by
t a p o e e t ca be ga ed by
performing local optimization
p
• DAG Representation of basic blocks
– A node for each initial values of the vars
– Node for each statement
• Children are the statements of the last definitions
• Labeled by operators and vars for which it is the last
definition in the block
– Some nodes are “output nodes” whose vars are live
on exit
• Part of global flow analysis, discussed later
Part of global flow analysis discussed later
Chapter 8: Code Generation CS5810 Spring 2009 19
DAGs for Basic Blocks
DAGs for Basic Blocks
c
+
a = b + c
‐ b,d
b = a – d
a
c = b + c + d0
d = a ‐ d b0 c0
Chapter 8: Code Generation CS5810 Spring 2009 20
Finding Local Common Subexpressions
Finding Local Common Subexpressions
c
+
a = b + c ‐ b,d a = b + c
b = a – d a d = a
d a–d
+ d0
c = b + c c = d + c
d = a ‐ d b0 c0
Chapter 8: Code Generation CS5810 Spring 2009 21
Dead Code Elimination
Dead Code Elimination
• Delete
Delete any root that has no live variables, and
any root that has no live variables and
repeat the procedure
e
a = b + c +
a b
b=b–d
b = b + ‐ +
c
c = c + d
e=b+c
e = b + c b0 c0 d0
Chapter 8: Code Generation CS5810 Spring 2009 22
Use of Algebraic Laws
Use of Algebraic Laws
• Identities
– x+0=0+x=x; x*1=1*x=x; x‐0=x; x/1=x;
• Reduction in strenth
– x2=x*x; 2*x = x+x; x/2=x*0.5
• Commutativity
– x*y=y*x
• Associativity
– a = b+c; e=c+d+b;
; ;
– a = b+c; t=c+d; e = t+b
– a = b + c; e = a+d
Chapter 8: Code Generation CS5810 Spring 2009 23
A Simple Code Generator
A Simple Code Generator
• Generate code for a single basic block
Generate code for a single basic block
• How to use registers?
– In most machine architectures, some or all of the
I t hi hit t ll f th
operands must be in registers
– Registers make good temporaries
Registers make good temporaries
– Hold values that are computed in one basic block
and used in other blocks
and used in other blocks
– Often used with run‐time storage management
Chapter 8: Code Generation CS5810 Spring 2008 24
Register and Address Descriptors
Register and Address Descriptors
• For
For each available register, a register
each available register a register
descriptor (RD) keeps track of the vars whose
current value in that register
current value in that register
– Initially empty
• For
For each var, an address descriptor (AD) keeps
each var an address descriptor (AD) keeps
track of the locations where the current value
of the var can be found
of the var can be found
– Location can be a register, a memory address, etc.
Chapter 8: Code Generation CS5810 Spring 2008 25
Code‐generation
Code generation Algorithm
Algorithm
• For a three‐address instruction, e.g. x=y+z
, g y
– Use getReg(x=y+z) to select registers Rx, Ry, Rz for x, y , z
– If y is not in Ry, issue an instruction LD Ry, y’
• Similarly for x
Si il l f
– Issue the instruction ADD Rx, Ry, Rz
• Copy statement x
Copy statement x=yy
– If y is not already in register, generate LD Ry, y’
– Adjust RD for Ry so it includes x
– Change AD for x so its only location is Ry
• Ending the basic block
– If x is used at other blocks, issue ST x, R
If x is used at other blocks issue ST x Rx
Chapter 8: Code Generation CS5810 Spring 2008 26
Managing Register and Address
Descriptors
• For LD R, x
For LD R x
– Change RD for R so it holds only x
– Change AD for x by adding R as an additional location
Change AD for x by adding R as an additional location
• For ST x, R
– Change AD for x to include its own memory location
Change AD for x to include its own memory location
• For ADD Rx, Ry, Rz
– Change
Change RD for R
RD for Rx so it holds only x
so it holds only x
– Change AD for x so its only location is Rx
– Remove R
Remove Rx from the AD of any var
from the AD of any var other than x
other than x
Chapter 8: Code Generation CS5810 Spring 2008 27
Example
t = a – b
u = a – c
v = t + u
a = d
d
d = v + u
• t, u, v are temp vars, while a, b, c, d are global
• Assume registers are enough
A it h
– Reuse registers whenever possible
Chapter 8: Code Generation CS5810 Spring 2008 28
Example
Example
R1 R2 R3 a b c d t u v
a b c d
t = a ‐ b LD R1 a; LD R2 b; SUB R2 R1 R2
LD R1, a; LD R2, b; SUB R2, R1, R2
R1 R2 R3 a b c d t u v
a t a,R1
, b c d R2
u = a ‐ c LD R3, c; SUB R1, R1, R3
R1 R2 R3 a b c d t u v
u t c a b c,R3 d R2 R1
Chapter 8: Code Generation CS5810 Spring 2008 29
v = t + u
t ADD R3, R2, R1
R1 R2 R3 a b c d t u v
u t v a b c d R2 R1 R3
a = d LD R2, d
R1 R2 R3 a b c d t u v
u a,d v R2 b c d,R2 R1 R3
Chapter 8: Code Generation CS5810 Spring 2008 30
d=v+u
d = v + u ADD R1 R3 R1
ADD R1, R3, R1
R1 R2 R3 a b c d t u v
d a v R2 b c R1 R3
ST a, R2; ST d, R1
R1 R2 R3 a b c d t u v
d a v a,R2 b c d,R1 R3
Chapter 8: Code Generation CS5810 Spring 2008 31
Function getReg
Function getReg
• Consider picking R
Consider picking Ry for y in x = y + z
for y in x = y + z
– If y in a register, do nothing
– If y not in a register and there is a empty one,
If y not in a register and there is a empty one
choose it as Ry
– Let v be one of the var
Let v be one of the var in R
in R
• We are OK if v is somewhere besides R
• We are OK if v is x
ea eO s
• We are OK if v is not used later
• Spill: ST v, R
Chapter 8: Code Generation CS5810 Spring 2008 32
Peephole Optimization
Peephole Optimization
• Exam
Exam a sliding window and replace instruction
a sliding window and replace instruction
sequence with a shorter or faster sequence
– Redundant‐instruction elimination
Redundant instruction elimination
– Flow‐of‐control optimization
– Algebraic simplifications
Algebraic simplifications
– Use a machine idioms
Chapter 8: Code Generation CS5810 Spring 2008 33
Eliminating Redundant Loads and
Stores
LD a, R0
ST R0, a
Chapter 8: Code Generation CS5810 Spring 2008 34
Eliminating Unreachable Code
Eliminating Unreachable Code
if debug==1 goto L1
if debug goto
goto L2
p gg g
L1: print debugging info
L2:
L2:
if debug!=1 goto L2
g g
L1: print debugging info
L2:
Chapter 8: Code Generation CS5810 Spring 2008 35
Flow‐of‐Control
Flow of Control Optimizations
Optimizations
g
goto L1 goto L2
… …
g
L1: goto L2 L1: goto L2
if a < b goto L1
if < b t L1 if a < b goto L2
if a < b goto L2
… …
L1 goto L2
L1: goto L2 L1: goto L2
L1: goto L2
Chapter 6: Intermediate Code
Chapter 8: Code Generation CS5810 Spring 2008 36
Generation
Optimal Code Generation for
Expressions
• We can choose registers optimally
We can choose registers optimally
– If a basic block consists of a single expression, or
– It is sufficient to generate code for a block one
It is sufficient to generate code for a block one
expression at a time
Chapter 8: Code Generation CS5810 Spring 2008 37
Ershov Numbers
• Assign
Assign the nodes of an expression tree a
the nodes of an expression tree a
number that tells how many registers needed
– Label leaf 1
Label leaf 1
– The label of an interior node with one child is the
label of its child
label of its child
– The label of an interior node with two children
• the larger one if the labels are different
the larger one if the labels are different
• One plus the label if the labels are the same
Chapter 8: Code Generation CS5810 Spring 2008 38
Ershov Numbers
t4
t1 t3
e t2
a b
c d
t1 = a – b
(a‐b)+e*(c+d)
(a b)+e (c+d) t2 = c + d
t2 = c + d
t3 = e * t2
t4 = t1 + t3
t4 = t1 + t3
Chapter 8: Code Generation CS5810 Spring 2008 39
Generating Code From Labeled
Expression Tree
• Recursive algorithm starting at the root
ecu s e a go t sta t g at t e oot
– Label k means k registers will be used
– Rb, Rb+1, …, Rb+k‐1 , where b>=1 is a base
• To generate machine code for a node with label k
and two children with equal labels
– Recursively generate code for the right child, using
base b+1: Rb+1, Rb+2, …, Result in Rb+k‐1
– Recursively generate code for the right child, using
Recursively generate code for the right child using
base b: Rb, Rb+1, …, Result in Rb+k‐2
– Generate instruction OP Rb+k‐1 , Rb+k‐2 ,Rb+k‐1
Chapter 8: Code Generation CS5810 Spring 2008 40
Generating Code From Labeled
Expression Tree
• To
To generate machine code for a node with
generate machine code for a node with
label k and two children with unequal labels
– Recursively generate code for the child with label
Recursively generate code for the child with label
k, using base b: Rb, Rb+1, …, Result in Rb+k‐1
– Recursively generate code for the child with label
Recursively generate code for the child with label
m, using base b: Rb, Rb+1, …, Result in Rb+m‐1
– Generate instruction OP R
Generate instruction OP Rb+k‐1
b+k 1 , R
, Rb+m‐1
b+m 1 ,Rb+k‐1
b+k 1
• For a leaf x, if base is b generate LD Rb, x
Chapter 8: Code Generation CS5810 Spring 2008 41
Ershov Numbers
t4
t1 t3
e t2
a b
c d
LD R3, d
LD R3 d
LD R2, c LD R2, b
ADD R3, R2, R3
ADD R3, R2, R3 LD R1 a
LD R1, a
LD R2, e SUB R2, R1, R2
MUL R3, R2, R3
MUL R3, R2, R3 ADD R3 R2 R3
ADD R3, R2, R3
Chapter 8: Code Generation CS5810 Spring 2008 42
Insufficient Supply of Registers
Insufficient Supply of Registers
• Input: a labeled tree and a number r of registers
put: a abe ed t ee a d a u be o eg ste s
• For a node N with at least one child labeled r or
g
greater
– recursively generate code for the big child with b=1.
The result will appear in Rr
– Generate machine instruction ST t
G hi i i ST k, RRr
– If the little child has label r or greater, b=1. If the label is
jj<r,
r, then b
then b=r‐j.
r j. The result in R
The result in Rr
– Generate the instruction LD Rr‐1, tk
– Generate OP Rr, Rr, Rr‐1 or OP Rr, Rr‐1, Rr
Chapter 8: Code Generation CS5810 Spring 2008 43
Insufficient Supply of Registers
Insufficient Supply of Registers
t4
t1 t3
e t2
a b
c d
LD R2, d
LD R1, c LD R2, b
ADD R2, R1, R2 ,
LD R1, a
LD R1, e SUB R2, R1, R2
MUL R2, R1, R2 LD R1, t3
,
ST t3, R2 ADD R2, R2, R1
Chapter 8: Code Generation CS5810 Spring 2008 44