IEEE SIGNAL PROCESSING LETTERS, VOL.

15, 2008 577

Fast Chirplet Transform With

FPGA-Based Implementation
Yufeng Lu, Member, IEEE, Erdal Oruklu, Member, IEEE, and Jafar Saniie, Senior Member, IEEE

Abstract—This letter presents a fast chirplet transform (FCT) Parameter estimation of chirp signals and derivation of several
algorithm, a computationally efficient method, for decomposing estimators were studied in [5].
highly convoluted signals into a linear expansion of chirplets. The Signal modeling and parameter estimation, although algo-
FCT algorithm successively estimates the chirplet parameters in
order to represent a broad range of chirplet shapes, including the rithmically complex and computationally heavy, can be an
broadband, narrowband, symmetric, skewed, nondispersive, or effective procedure to decompose and estimate echoes with
dispersive. These parameters have significant physical interpre- important diagnostic information. The parameters of a chirplet,
tations for radar, sonar, seismic, and ultrasonic applications. For i.e., time-of-arrival, center frequency, amplitude, bandwidth
the real-time application and embedded implementation of the factor, chirp rate, and phase, are capable of representing a
FCT algorithm, an FPGA-based hardware/software co-design is broad range of echo shapes, including the narrowband, broad-
developed on Xilinx Virtex-II Pro FPGA development platform.
Based on the balance among the system constraints, cost, and the band, symmetric, skewed, nondispersive, or dispersive [6].
efficiency of estimations, the performance of different algorithm The chirplet parameter estimator is an unbiased and minimum
implementation schemes have been explored. The developed variance estimator. Moreover, the estimated parameters closely
system-on-chip successfully exhibits robustness in the chirplet represent the physical properties of the system, such as position
transform of experimental signals. The FCT algorithm addresses and velocity of a target in radar or sonar, target size, and orien-
a broad range of applications including velocity measurement,
target detection, deconvolution, object classification, data com-
tation in ultrasonic imaging. In this letter, we present a highly
pression, and pattern recognition. efficient realization of chirplet transform and also an embedded
system running on an FPGA.
Index Terms—Detection, estimation, fast chirplet transform, In the following section, the fast chirplet transform (FCT) al-
field programmable gate arrays, hardware/software co-design.
gorithm and the procedure for successive parameter estimation
is presented. Section III discusses hardware/software (HW/SW)
co-design of an FPGA-system for the FCT algorithm. Moreover,
I. INTRODUCTION
a case study of the FPGA system using an ultrasonic experi-
mental signal and a bat chirp signal is presented.

I N RADAR, sonar, speech processing, seismic exploration,

and ultrasound applications, the detected echoes are often
nonstationary and corrupted by the measurement noise and/or
II. CHIRPLET TRANSFORM
undesired scattering echoes (clutter). Consequently, isolating In most detection applications, a single echo can be modeled
these echoes becomes a challenging problem, and conventional as a chirplet [6], [7] as follows:
signal analysis techniques fails to unravel the desired signal
information necessary for target detection, speech analysis,
seismic reflections, and ultrasonic imaging. The chirplet is (1)
a type of signal often encountered in radar applications [1].
Chirplet transform was introduced in [2] as an expansion of where denotes the parameter vector.
arbitrary function onto a basis of multiscale chirps, and it was The term is the time-of-arrival, is the center frequency,
used for detection of floating objects in marine radar applica- is the amplitude, is the chirp rate, is the phase, and is
tions. In [3], a chirplet-based adaptive signal representation the bandwidth factor of the echo. The chirplet transform of the
algorithm was applied to extract features from ISAR data of a echo is defined as [2], [6] follows:
target with a rigid main body and a rotating part. Similarly, the
chirplet transform was used for seismic event recognition and (2)
extracting time-varying information from seismic records [4].
where
Manuscript received December 26, 2007; revised March 15, 2008. The as-
sociate editor coordinating the review of this manuscript and approving it for
publication was Dr. Athanassios Skodras.
Y. Lu is with the Electrical and Computer Engineering Department, Bradley
University, Peoria, IL 61625 USA (e-mail: [email protected]).
E. Oruklu and J. Saniie are with the Electrical and Computer. Engineering (3)
Department, Illinois Institute of Technology, Chicago, IL 60616 USA (e-mail:
[email protected]; [email protected]).
Color versions of one or more of the figures in this letter are available online denotes the chirplet kernel, and
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LSP.2008.2001816

1070-9908/$25.00 © 2008 IEEE

578 IEEE SIGNAL PROCESSING LETTERS, VOL. 15, 2008

denotes the parameter vector of the chirplet used for transforma-

tion. The parameter can be successively estimated [6] as shown
in the following:

(4)

(5)

(6)

(7)

The objective of the FCT algorithm is to decompose the

signal, , into a linear expansion of chirplets and efficiently
estimate the parameter vectors defining these chirplets (this is
also known as adaptive chirplet transform ACT [8])

(8)

The parameter vector can be estimated based on the

chirplet transform of the signal . By localizing the dom-
inant echo in a time-frequency representation of the signal
(i.e., chirplet transform), we can estimate the time-of-arrival,
center frequency, and amplitude of the dominant echo and
then successively estimate the remaining parameters [6]. In an
iterative manner, the residual signal is obtained by subtracting
the estimated single dominant echo from the signal. The de-
composition process is repeated until the energy of residual
signal reaches below a predefined reconstruction condition.
The chirplet transform algorithm is capable of achieving a
high-resolution time-frequency representation and accurate es-
timation of parameters. Nevertheless, the time-frequency repre-
sentation used for decomposition in the algorithm is computa- Fig. 1. Flow chart of the FCT algorithm.
tionally heavy due to chirplet transform. In each iteration stage,
the entire chirplet transform matrix is generated for the echo
isolation process, which hinders the algorithm from real-time 3) Estimate the time-of-arrival which maximizes the chirplet
signal processing applications. This problem can be overcome transform, given the estimated center frequency from the
by utilizing a fast implementation scheme of the algorithm. In- previous step.
stead of two-dimensional transform, we use one-dimensional 4) Estimate the center frequency which maximizes the
transform and iteratively estimate the time-of-arrival, center fre- chirplet transform, given the new estimated time-of-arrival
quency, and amplitude of the dominant echo. Fig. 1 shows the from Step 3.
flow chart of the FCT algorithm. The steps involved in the itera- 5) Check convergence: If and (here,
tive estimation of an experimental signal are outlined as follows. and are predefined convergence conditions), then
1) Find the maximum location of in time domain and go to Step 6; otherwise, go to Step 3.
use it as the initial guess of time-of-arrival and the starting 6) Estimate the amplitude and the remaining parameters
point of iteration. , and successively.
2) Estimate the center frequency which maximizes the 7) Obtain the residual signal by subtracting the estimated
chirplet transform, given initial guess of time-of-arrival. echo from the signal.
LU et al.: FAST CHIRPLET TRANSFORM WITH FPGA-BASED IMPLEMENTATION 579

8) Calculate energy of the residual signal and check con- TABLE I

vergence ( is predefined convergence condition): If PERFORMANCE COMPARISON OF SCHEME 1–SCHEME 4
, STOP; otherwise, go to Step 1.
From the above steps, it can be seen that the FCT algorithm
significantly relaxes the computation load of the algorithm.

III. FPGA-BASED HARDWARE/SOFTWARE CO-DESIGN

The FCT algorithm has been implemented as a system-on-
chip (SoC) based on a Xilinx Virtex II Pro FPGA to explore its For the software optimization, the embedded processor
suitability for real-time applications. FPGA has been chosen IP core (PowerPC 405) can be used with an optional and
due to its reconfigurable and reprogrammable ability. From the size-configurable instruction cache and data cache for im-
system point of view, the FPGA-based SoC design consists proved performance. The FCT algorithm has been successfully
of two parts: hardware architecture and software code, where implemented on the embedded PowerPC405 core of XUP-V2P
hardware architecture is a structured combination of processing (Xilinx Virtex-II Pro FPGA development system) [10]. The
elements (including hard/soft processor core, IP cores, and signal source used in the embedded system is from an appli-
hardware accelerators), and external interfaces to different cation of ultrasonic target detection [6]. The center frequency
I/Os (such as UART, Ethernet, USB, and VGA, etc.), and the of the ultrasonic transducer is 5 MHz and the sampling rate
software part is the executable code running on the on-chip is 100 MHz. A 512-point experimental data set is used to test
processor. the performance of FCT algorithm on this system. The effort
The objective of the design is to partition the FCT algorithm of acceleration and optimization varies in the different stages
into hardware and software components based on their compu- of hardware/software co-design. Four implementation schemes
tational demands. The profiling results of the FCT algorithm re- have been prototyped. These implementation schemes are:
vealed that several computationally intensive functions cost a Scheme 1: Software implementation on PowerPC405;
significant amount of the execution time. These functions and Scheme 2: Scheme 1 with data and instruction caching;
their associated percent execution time are: Scheme 3: Scheme 2 plus hardware multiplier accelerator,
Est T : estimate time-of-arrival given the center frequency software look-up tables for trigonometric, and exponential
(see step 3 of the FCT algorithm). Execution time: 24%. functions;
Est F : estimate frequency given the time-of-arrival (see Scheme 4: Scheme 3 with hardware FFT accelerator.
step 4 of the FCT algorithm). Execution time: 39%. The performance for these four schemes is presented in
Est Para: estimate the remaining parameters of chirplets Table I. Caching a small size of local memory in the processor
(see step 6 of the FCT algorithm). Execution time: 36%. core can boost the performance of CPU and save the time of
It can be seen that these functions comprise around 99% of accessing data and instruction by buffering recent visited data
the total execution time, and they are good candidates for hard- or instructions. The caching effect can be examined from the
ware accelerators and/or software optimization. Further analysis system performance of Schemes 1 and 2. It can be seen that the
shows that calculating multiplications, trigonometric, exponen- overall performance of FCT algorithm is increased 22.6 times
tial, and FFT functions take most of the execution time in im- by enabling the data and instruction caching of the embedded
plementing the FCT algorithm. For example, FFT function ac- PowerPC405 processor.
counts for 68% of Est T and 12% of Est Para execution times. As discussed in the profiling results of the algorithm, the
To implement the hardware accelerator, the challenge is to sub- Est F function is more dependent on the efficiency of multiplier,
stitute the function in the software implementation with the code trigonometric, and exponential functions; the Est T function
to access the accelerator. Xilinx core generator system provides heavily depends on the computation of FFT; the computation of
a catalog of user-customizable cores to streamline the design Est Para is more evenly distributed on FFT and trigonometric
process and improve design quality on Xilinx FPGA devices. functions.
For the FFT function, we use the FFT core with run-time pro- In Scheme 3, the hardware multipliers and software look-up
grammable transform size and streaming pipeline implementa- tables are used to accelerate the algorithm. Compared with
tion. Multiplier core is chosen to implement the multiplier func- Scheme 2, the execution time of Est F is significantly improved
tions. Exponential function can be implemented in hardware [9]. by 60.8 times in Scheme 3; whereas, the Est T only gains
However, the performance improvement through hardware ac- performance improvement by 3.6 times in Scheme 3. This is
celerator for exponential function becomes limited due to ac- confirmed by the inspection of the algorithm: the Est F is more
cess-time overhead. It is important to point out that the chirplet dependent on the efficiency of the multiplier, trigonometric,
transform is only applicable to band-limited signals, and this and exponential functions.
allows an efficient and practical use of software look-up table As a comparison, in Scheme 4, a hardware FFT core is used
to implement the exponential function, which is a to accelerate the system, especially the Est T and Est Para
monotonic decreasing function for . Similarly, we uti- functions. As expected, the FFT accelerator has no effect
lize look-up tables and the existing multiplier cores within the on the performance of the Est F function since there is no
FPGA to calculate the phase (i.e., ) FFT operation in Est F function. The execution time of Est T
and to obtain the values of trigonometric functions. function is improved by 12.3 times, compared with the one
580 IEEE SIGNAL PROCESSING LETTERS, VOL. 15, 2008

Fig. 2. Ultrasonic backscattered signal superimposed with the reconstruction Fig. 3. Bat chirp signal superimposed with the reconstructed echoes.
echoes.

IV. CONCLUSION
in Scheme 3. The Est Para gets a moderate performance gain
from the FFT accelerator. It can be seen that the overall per- In this letter, an FPGA-based hardware/software co-design
formance of the FCT algorithm has been improved by 775.45 for the fast chirplet transform algorithm is presented. The pro-
times through the FPGA-based hardware/software co-design. totype design shows that hardware accelerators and software op-
The performance improvement from hardware accelerator timization have improved the system performance significantly.
comes at the expense of logic usage in FPGA. In the embedded The developed embedded system successfully decomposed the
ultrasonic experimental data and bat chirp signal into chirplets
implementations of the FCT algorithm, the trade-off between
and estimated all the parameters. This type of study addresses a
performance and logic usage for Schemes 1 and 3 is: 5.1%
broad range of applications in target detection, deconvolution,
more number of logic slices, 3.2% more number of slice flip
object classification, data compression, and pattern recognition.
flops, and 4.3% more number of four-input LUTs due to the
multiplier hardware accelerators. The trade-off for Schemes 3
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