EASWARI ENGINEERING COLLEGE

(Autonomous)
Bharathi Salai, Ramapuram, Chennai – 600 089

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

Laboratory Workbook / Observation

Academic Year: 2022 – 2023 / Even Semester

191ECC611L: VLSI DESIGN LABORATORY

Name of the Student : _________________________

Register Number : _________________________
Year / Semester / Section : _________________________

1
2
 SYLLABUS
L T P R C
191ECC611L VLSI DESIGN LABORATORY
0 0 3 1 2

OBJECTIVES:

➢ To learn Hardware Descriptive Language (Verilog/VHDL)

➢ To learn the fundamental principles of VLSI circuit design in digital and analog domain
➢ To familiarize fusing of logical modules on FPGAs
➢ To provide hands on design experience with professional design (EDA) platforms

LIST OF EXPERIMENTS:

Part I: Design the following Digital System using HDL &Implement by Altera/Altera FPGA
(36 Periods)

1. Adder – Ripple Carry Adder/ Carry Lookahead Adder (Minimum 8 Bit)

2. Multiplier – Booth Multiplier/ Wallace Tree Multiplier/Array Multiplier (4 Bit Minimum)
3. Comparators, Decoders, Multiplexers and Demultiplexers
4. Arithmetic & Logic Unit (4 bit Minimum)
5. Latches & Flip-Flops
6. Universal Shift Register (4 bit Minimum)
7. Synchronous Counters (4 bit)
8. Finite State Machine (Moore/Mealy)
9. Random Access Memory(4x4)
Requirements for Part I: Altera ISE/Altera Quartus/ equivalent EDA Tools along with
Altera/Altera/equivalent FPGA Boards

Part-II Analog Circuit Design (24 Periods)

10. Design and Simulate a CMOS Inverter by performing Schematic Simulations.

11. Design and simulate simple 5 transistor differential amplifier. Analyze Gain, Bandwidth and
CMRR by performing Schematic Simulations.
12. Design, Simulate and Extract the layout of a CMOS Inverter
Requirements for Part II: Cadence/Synopsis/ Mentor Graphics/Tanner/equivalent EDA Tools

TOTAL :60 PERIODS

3
OUTCOMES:
At the end of the course, the student should be able to:
➢ Write HDL code for basic as well as advanced digital integrated circuit
➢ Import the logic modules into FPGA Boards
➢ Synthesize Place and Route the digital IPs
➢ Design, Simulate and Extract the layouts of Digital & Analog IC Blocks using EDA tools

4
LIST OF EXPERIMENTS

CYCLE-I

1. Design, Simulation & Implementation of Logic Gates

2. Design, Simulation & Implementation of Half Adder and Full Adder
3. Design, Simulation & Implementation of 8 Bit Ripple Carry Adder
4. Design, Simulation & Implementation of 4 Bit Array Multiplier
5. Design, Simulation & Implementation of Comparators, Decoders, Multiplexers
and Demultiplexers
6. Design, Simulation & Implementation of 8 Bit Arithmetic and Logic Unit
7. Design, Simulation & Implementation of Latches & Flip Flops
8. Design, Simulation & Implementation of Universal Shift Register
9. Design, Simulation & Implementation of Synchronous Up Down Counter
10. Design, Simulation & Implementation of Finite State Machines
11. Design, Simulation & Implementation of Random-Access Memory

CYCLE-II

12. Transistor level Simulation of CMOS Inverter

13. Transistor level Simulation of Differential amplifier
14. Layout Extraction CMOS Inverter

EXPERIMENT BEYOND THE SYLLABUS

15. Domino Logic circuit simulation using EDA Tool

5
 INDEX

EX. No. DATE NAME OF THE EXPERIMENT MARKS SIGN

6
EX. No. DATE NAME OF THE EXPERIMENT MARKS SIGN

Completion date Marks awarded /10 Faculty Signature

7
 EASWARI ENGINEERING COLLEGE (AUTONOMOUS)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
COURSE PLAN
REGULATION – 2019

Total no. of hours given in

Course/Branch : B.E. / ECE
syllabus:
Subject Code : 191ECC611L Lecture : -
Subject Title : VLSI DESIGN LABORATORY Tutorials : -
Year/Semester : III / VI Practical : 60
Dr.O.Vignesh, Asst.Prof/ECE :

Faculty Name : Dr.S.R.Sriram, Asst.Prof/ECE TOTAL 60

Mr.B.Arivuselvam, Asst.Prof/ECE

COURSE OBJECTIVES:

➢ To learn Hardware Descriptive Language (Verilog/VHDL)

➢ To learn the fundamental principles of VLSI circuit design in digital and analog domain
➢ To familiarize fusing of logical modules on FPGAs
➢ To provide hands on design experience with professional design (EDA) platforms

S.NO NAME OF THE EXPERIMENT No. of

hours
1 DESIGN, SIMULATION & IMPLEMENTATION OF LOGIC GATES 4
2 DESIGN, SIMULATION & IMPLEMENTATION OF HALF ADDER AND FULL ADDER 4
3 DESIGN, SIMULATION & IMPLEMENTATION OF 8 BIT RIPPLE CARRY ADDER 4
4 DESIGN, SIMULATION & IMPLEMENTATION OF 4 BIT ARRAY MULTIPLIER 4
5 DESIGN, SIMULATION & IMPLEMENTATION OF COMPARATORS, DECODERS, 4
MULTIPLEXERS AND DEMULTIPLEXERS
6 DESIGN, SIMULATION & IMPLEMENTATION OF 8 BIT ARITHMETIC AND LOGIC UNIT 4
7 DESIGN, SIMULATION & IMPLEMENTATION OF LATCHES & FLIP FLOPS 4
8 DESIGN, SIMULATION & IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER 4
9 DESIGN, SIMULATION & IMPLEMENTATION OF UP DOWN COUNTER 4
10 DESIGN, SIMULATION & IMPLEMENTATION OF STATE MACHINES 4
11 DESIGN, SIMULATION & IMPLEMENTATION OF RANDOM-ACCESS MEMORY 4
12 TRANSISTOR LEVEL SIMULATION OF CMOS INVERTER 4
13 TRANSISTOR LEVEL SIMULATION OF DIFFERENTIAL AMPLIFIER 4
14 LAYOUT EXTRACTION OF CMOS INVERTER 4

EXPERIMENT BEYOND THE SYLLABUS

15 DOMINO LOGIC CIRCUIT SIMULATION USING EDA TOOL 4

TOTAL HOURS 60

8
Course Outcomes:
Students must be able to
191ECC611L.1: Model a digital circuit using Verilog HDL and validate its functionality
191ECC611L.2: Import the logic modules into FPGA Boards
191ECC611L.3: Analyse the VLSI entities from synthesis report
191ECC611L.4: Simulate a CMOS circuit in Transistor level
191ECC611L.5: Analyze Gain, Bandwidth and CMRR of Differential amplifier by performing
Schematic Simulations
191ECC611L 6: Develop the layout for CMOS designs in GDS II file format

Program Outcomes:
PO1: Engineering Knowledge
PO2: Problem Analysis
PO3: Design/Development of Solutions
PO4: Conduct investigations of complex problems
PO5: Modern Tool Usage
PO6: The Engineer and Society
PO7: Environment and Sustainability
PO8: Ethics
PO9: Individual and Team Work
PO10: Communication
PO11: Project Management and Finance
PO12: Life Long Learning

PROGRAM SPECIFIC OUTCOMES:

PSO1: To design and construct analog and digital circuits and to simulate the integrated circuits with
software tools which lead to the development of electronic gadgets.
PSO2: To design and analyze various signal & image processing blocks for communication areas and
to implement their professional skills and techniques in network fields which are applicable to
industrial and societal needs.

MAPPING OF COURSE OUTCOMES WITH THE PROGRAM OBJECTIVES:

CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12

191ECC611L.1 3 3 3 3 3 3 - - 3 - - 2

191ECC611L.2 3 3 3 3 3 3 - - 3 - - 3

191ECC611L.3 3 3 3 3 3 2 - - 3 - - 1

191ECC611L.4 3 3 3 3 3 2 - - 3 - - 2

191ECC611L.5 3 3 3 3 3 3 - - 3 - - 1

191ECC611L.6 3 3 3 3 3 3 - - 3 - - 3

191ECC611L 3 3 3 3 3 2.6 - - 3 - - 2

9
Justification of the mapping:
191ECC611L.1 An in-depth knowledge of mathematics and engineering is required to understand the
basics of digital integrated circuits (PO1). Problems on integrated circuits can be
formulated and analyzed with the fundamentals learnt (PO2). It inculcates the ability
to develop solutions using HDL for complex circuit design (PO3) through
experimentation (PO4) and CAD tools (PO5). Weak updation with the recent trends
(PO12).
191ECC611L.2 A good mathematical and engineering fundamental is required to import logic
modules into FPGA (PO1). Weak impact to the formulation of problems related to
FPGA implementation (PO2). Less chances of developing solutions to logic
implementation by conducting experiments (PO4) and thereby develop solutions to
cater to the societal needs (PO3). Usage of CAD tools (PO5) is needed to indulge in
persistent learning (PO12).
191ECC611L.3 Adequate ability is acquired to synthesize, Place and route digital IPs through
competent comprehension of necessary mathematics and engineering concepts
(PO1). With the knowledge assimilated, problems related to implementation are
seldom identified and analyzed (PO2). Design of ICs can be rarely done by
performing experiments (PO4) to cater to the societal needs (PO3). Usage of CAD
tools (PO5) is essential to engage in long-term study (PO12).
191ECC611L.4 Engineering and mathematical background is essential to design, simulate CMOS
circuit (PO1). CMOS circuit simulation identified (PO2) to develop solutions for
societal requirements (PO3) by conducting experiments (PO4). Analog IC simulation
tools are utilized to observe the parameters of various IC designs (PO5) and gain a
lasting experience (PO12).
191ECC611L.5 Parameter analysis thorough schematic design simulation involves understanding of
mathematics and the engineering concepts learnt (PO1) to formulate the selection of
appropriate circuits in IC design (PO2). Rarely Conclusions are derived through
experiments (PO4) are utilized to design application-specific ICs (PO3) with the aid
of specific CAD tools (PO5). An overall scope for updating the technological
changes (PO12) is possible.
191ECC611L.6 Competent analytical and engineering knowledge is needed to comprehend Digital
IC design (PO1). Problems encountered during the layout generation and extraction
are identified in the implementation phase (PO2) is analyzed with modern tools
(PO5) and moderate solutions are developed (PO3) through experimentation (PO4).
Henceforth an overall interested is inculcated to stay updated with the latest trends
(PO12).

MAPPING OF COURSE OUTCOMES WITH THE PROGRAM SPECIFIC OUTCOMES:

CO PSO1 PSO2
191ECC611L.1 3 3
191ECC611L.2 3 3
191ECC611L.3 3 3
191ECC611L.4 3 3
191ECC611L.5 3 3
191ECC611L.6 3 3
191ECC611L 3 3

10
Justification of the mapping:
191ECC611L.1 An indepth knowledge of Digital circuit design (PSO1) and very less impact on
signal, Image processing and also in communication networks and an overall ability
to design ICs to meet industrial & societal needs (PSO2).
191ECC611L.2 Basic knowledge about logic modules is required for implementation (PSO1) and
meagre impact on signal, Image processing and also in communication networks and
an overall ability to develop FPGA to meet industrial & societal needs (PSO2).
191ECC611L.3 Basic knowledge about digital modules is required for routing (PSO1) and meagre
impact on signal, Image processing and also in communication networks and an
overall ability to develop solutions in the synthesize of digital ICs to meet industrial
& societal needs (PSO2).
191ECC611L.4 An in depth knowledge of CMOS circuit design (PSO1) and impact on signal, Image
processing and also in communication networks and an overall ability to develop ICs
using EDA tools to meet industrial & societal needs (PSO2).
191ECC611L.5 An in depth knowledge of Differential amplifier circuit design (PSO1) and very less
impact on signal, Image processing and also in communication networks and an
overall ability to develop digital ICs using EDA tools to meet industrial & societal
needs (PSO2).
191ECC611L.6 Detailed knowledge of layout extraction (PSO1) and very less impact on signal,
Image processing and also in communication networks and an overall ability to
obtain GDS II to meet industrial & societal needs (PSO2).

EXPERIMENT BEYOND SYLLABUS:

Sl. No. Name of the Experiment PO PSO

1 DOMINO LOGIC IMPLEMENTATION USING SPICE 1,2
TOOL 7,9,11

11
12
 DESIGN, SIMULATION & IMPLEMENTATION
Exp. No. : 1 Date:
OF LOGIC GATES

AIM:
To design, simulate and implement the logic gates in Altera Quartus and obtain the simulated results
using Verilog HDL.

APPARATUS REQUIRED:
1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or behavioural level).
4. Enter the Verilog code in Altera software using the steps given below.
5. Check the syntax and simulate the above verilog code using Altera and
verify the functionality of the circuit with its simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and verify the
functionality of the circuit.

Logic Diagram

AND gate

OR gate

13
NOT gate

NAND gate

NOR gate

EXOR gate

EXNOR gate

14
PROGRAM
Structural Test Bench
module gatessvvy( module gatesvvyv;
input a,b, // Inputs
output c,d,e,f,g,h reg a;
); reg b;
and g1(c,a,b); // Outputs
or g2(d,a,b); wire c;
not g3(e,a); wire d;
nand g4(f,a,b); wire e;
nor g5(g,a,b); wire f;
xor g6(h,a,b); wire g;
endmodule wire h;
// Instantiate the Unit Under Test (UUT)
gatessvvy uut (
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.h(h)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100;
a = 0;
b = 1;
#100;
a = 1;
b = 0;
#100;
a = 1;
b = 1;
// Add stimulus here
end
endmodule

15
SIMULATED RESULTS:

RTL Schematic Representation-Top Level

16
RTL Schematic Representation-Gate Level

RESULT:

17
18
 DESIGN, SIMULATION & IMPLEMENTATION OF
Exp. No. : 2 Date:
HALF ADDER AND FULL ADDER

AIM:
To design, simulate and implement the half and full adder in Altera Quartus and obtain the
simulated results using Verilog HDL.

APPARATUS REQUIRED:

1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or behavioural level).
4. Enter the Verilog code in Altera software using the steps given below.
5. Check the syntax and simulate the above verilog code using Altera and verify the
functionality of the circuit with its simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and verify the
functionality of the circuit.

THEORY:

HALF ADDER:
The half adder consists of two input variables designated as Augends and Addend bits.
Output variables produce the Sum and Carry. The ‘carry’ output is 1 only when both inputs are 1
and, sum’ is 1 if any one input is 1. The Boolean expression is given by,
sum = x ^ y carry
=x&y

FULL ADDER:
A Full adder is a combinational circuit that focuses the arithmetic sum of three bits. It
consists of 3 inputs and 2 outputs. The third input is the carry from the previous Lower Significant
Position. The two outputs are designated as Sum (S) and Carry (C). The binary variable S gives the
value of the LSB of the Sum. The output S=1 only if odd number of 1’s is present in the input and
the output C=1 if two or three inputs are 1.
sum = x ^ y ^ z
carry= (x & y) | (y & z) | (x & z)
19
LOGIC DIAGRAM: TRUTH TABLE:
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

PROGRAM :

HALF ADDER:

Structural Data-Flow Behavioral

module module HA(a,b,sum,carry); module HA(a,b,sum,carry);
HA(a,b,sum,carry); input a,b; input a,b;
input a,b; output sum,carry; output sum,carry;
output sum,carry; assign sum=a^b; always@ (a or b)
xor (sum,a,b); assign carry=a&b; begin
and (carry,a,b); endmodule sum=a^b;
endmodule carry=a&b;
end
endmodule

SIMULATED RESULTS:

20
RTL Schematic Representation-Top Level

RTL Schematic Representation-Gate Level

FULL ADDER:

Structural Data-Flow Behavioral

module fast(a, b,c, sum, module fada(a, b, c, sum, carry); module fabe(a, b, c, sum, carry);
carry); input a; input a;
input a; input b; input b;
input b; input c; input c;
input c; output sum; output sum;
output sum; output carry; output carry;
output carry; wire w1,w2,w3; reg sum, carry, w1, w2, w3;
wire w1,w2,w3,w4; assign sum=(a^b)^c; always @(a or b or c)
xor(w4,a,b); assign w1=a&b; begin
xor(sum,w4,c); assign w2=a&c; sum=(a^b)^c;
and(w1,a,b); assign w3=b&c; w1=a&b;
and (w2,a,c); assign carry=(w1|w2)|w3; w2=a&c;
and(w3,b,c); endmodule w3=b&c;
or(carry,w1,w2,w3); carry=(w1|w2)|w3;
endmodule end
endmodule

21
SIMULATED RESULTS:

RTL Schematic Representation-Top Level

RTL Schematic Representation-Gate Level

Result:

22
 DESIGN, SIMULATION &
Exp. No. : 3 IMPLEMENTATION OF 8 BIT RIPPLE Date:
CARRY ADDER

AIM:
To design, simulate and implement the 8 Bit ripple carry adder and obtain the simulated results
using Verilog HDL in Altera Quartus.

APPARATUS REQUIRED:

1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or behavioural level).
4. Enter the Verilog code in Altera software using the steps given below.
5. Check the syntax and simulate the above verilog code using Altera and verify the
functionality of the circuit with its simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and verify the
functionality of the circuit.

BLOCK DIAGRAM:

23
TRUTH TABLE:

A B Cin Sum Carry

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
PROGRAM:
DATA FLOW STRUCTURAL BEHAVIORAL
module rrd(a, b, cin, sum, cout); module RIP(a, b, cin, cout, sum); module rrd(a, b, cin,
input [7:0] a; input [7:0] a; sum, cout);
input [7:0] b; input [7:0] b; input [7:0] a;
input cin; input cin; input [7:0] b;
output [7:0] sum; output cout; input cin;
output cout; output [7:0] sum; output [7:0] sum;
assign {cout,sum}=a+b+cin; wire c1,c2,c3,c4,c5,c6,c7; output cout;
endmodule faas n1(a[0],b[0],cin,sum[0],c1); reg [7:0]sum;
faas n2(a[1],b[1],c1,sum[1],c2); reg cout;
faas n3(a[2],b[2],c2,sum[2],c3); reg [7:0]temp;
faasn4(a[3],b[3],c3,sum[3],c4); always@(a or b or cin)
faasn5(a[4],b[4],c4,sum[4],c5); begin
faasn6(a[5],b[5],c5,sum[5],c6); temp=a+b+cin;
faasn7(a[6],b[6],c6,sum[6],c7); sum=temp[7:0];
faasn4(a[7],b[7],c7,sum[7],cout); cout=temp[8];
endmodule end
module faas(x,y,z, sum, carry); endmodule
input x;
input y;
input z;
output sum;
output carry;
wire w1,w2,w3;
xor(w1,x,y);
xor(sum,w1,z);
and(w2,x,y);
and(w3,w1,z);
or(carry,w3,w2);
endmodule

24
SIMULATED RESULTS:

RESULT:

25
26
 DESIGN, SIMULATION & IMPLEMENTATION OF
Exp. No. : 4 Date:
4 BIT ARRAY MULTIPLIER

AIM:
To design and simulate a 4*4 Array Multiplier in Altera ISE13.2 and obtain the waveforms.

APPARATUS REQUIRED:

1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or behavioural level).
4. Enter the Verilog code in Altera software using the steps given below.
5. Check the syntax and simulate the above verilog code using Altera and
verify the functionality of the circuit with its simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and
verify the functionality of the circuit.

PROGRAM:

27
SIMULATED RESULTS:

RESULT:

28
 DESIGN, SIMULATION & IMPLEMENTATION OF
COMPARATORS, DECODERS, MULTIPLEXERS
Exp. No.: 5 Date:
AND DEMULTIPLEXERS

AIM :
To design, simulate and implement the Comparators, Decoders, Multiplexers And
Demultiplexers using Altera ISE13.2 and obtain the simulated results of the same.

APPARATUS REQUIRED:

1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or behavioural level).
4. Enter the Verilog code in Altera software using the steps given below.
5. Check the syntax and simulate the above verilog code using Altera and verify the
functionality of the circuit with its simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and
verify the functionality of the circuit.

2-Bit Magnitude Comparator :

A comparator used to compare two binary numbers each of two bits is called a 2-bit
magnitude comparator. It consists of four inputs and three outputs to generate less than, equal
to and greater than between two binary numbers.
Truth table for a 2-bit comparator

29
From the above truth table logical expressions for each output can be expressed as follows:
A > B : A1B1’ + A0B1’B0’ + A1A0B0’
A = B : A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A < B : A1’B1 + A0’B1B0 + A1’A0’B0

By using these Boolean expressions, we can implement a logic circuit for this comparator as
given:
Logic Diagram for a 2-bit comparator

Verilog code for 2-bit Magnitude Comparator

30
Simulation results:

2x4 Decoder
The name “Decoder” means to translate or decode coded information from one format into
another, so a digital decoder transforms a set of digital input signals into an equivalent
decimal code at its output
A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of m=2^n unique output lines.

Block Diagram of 2-to-4 Decoder

Logic Diagram of 2-to-4 Decoder

31
Verilog code for 2-4 Decoder

Simulation Results

4x1 Multiplexer
4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two selection lines S0 & S1 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.One of
these 4 inputs will be connected to the output based on the combination of inputs present at
these two selection lines. Truth table of 4x1 Multiplexer is shown below.

32
Block diagram of 4x1 Multiplexer

Truth Table of 4x1 Multiplexer

Verilog Code for 4x1 Multiplexer

33
Simulated Results

1x4 De-multiplexer

1x4 De-Multiplexer has one input Data(D), two selection lines, S0 & S1 and four outputs Y0,
Y1, Y2 & Y3. The block diagram of 1x4 De-Multiplexer is shown in the following figure.

Block diagram of 1x4 De-Multiplexer

Truth table of 1x4 De-Multiplexer

34
Logic diagram of 1x4 De-Multiplexer

Verilog Code for 1x4 De-Multiplexer

35
Simulated Results

Result :

36
 DESIGN, SIMULATION & IMPLEMENTATION OF
Exp. No. : 6 Date:
8 BIT ARITHMETIC AND LOGIC UNIT
AIM :
To design, simulate and implement the 8 Bit Arithmetic and logic unit using Altera ISE13.2
and obtain the simulated results of the same.

APPARATUS REQUIRED:

4. Personal Computer
5. ALTERA QUARTUS II
6. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

7. Draw the logic diagram for the given combinational circuit.

8. Write the truth table.
9. Write the Verilog code (Gate level or Data flow level or behavioural level).
10. Enter the Verilog code in Altera software using the steps given below.
11. Check the syntax and simulate the above verilog code using Altera and verify the
functionality of the circuit with its simulated output waveform.
12. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and
verify the functionality of the circuit.

Theory
An arithmetic logic unit (ALU) is a combinational digital electronic circuit that
performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to
a floating-point unit (FPU), which operates on floating point numbers. An ALU is a
fundamental building block of many types of computing circuits, including the central
processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). A single
CPU, FPU or GPU may contain multiple ALUs.
The inputs to an ALU are the data to be operated on, called operands, and a code indicating
the operation to be performed; the ALU's output is the result of the performed operation. In

37
many designs, the ALU also has status inputs or outputs, or both, which convey information
about a previous operation or the current operation, respectively, between the ALU and
external status registers.

PROGRAM

SIMULATED RESULTS

RESULT

38
 DESIGN, SIMULATION &
Exp. No. : 7 Date:
IMPLEMENTATION OF FLIP FLOPS

AIM :
To design, simulate and implement the différent types of Flip Flops using Altera
ISE13.2 and obitain the simulated results of the same.

APPARATUS REQUIRED:

1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or behavioural level).
4. Enter the Verilog code in Altera software using the steps given below.
5. Check the syntax and simulate the above verilog code using Altera and verify the
functionality of the circuit with its simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and
verify the functionality of the circuit

1) D-FLIP FLOP

LOGIC DIAGRAM: TRUTH TABLE:

Q(t) D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1

PROGRAM:

39
SIMULATED RESULTS

2) T-FLIP FLOP

LOGIC DIAGRAM : TRUTH TABLE:

Q(t) T Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0

PROGRAM:

40
SIMULATED RESULTS

3) JK FLIP FLOP

PROGRAM:

41
SIMULATED RESULTS

RESULT:

42
 DESIGN, SIMULATION &
Exp. No. : 8 IMPLEMENTATION OF UNIVERSAL Date:
SHIFT REGISTER

AIM :
To design, simulate and implement the Universal Shift register using Altera ISE13.2
and obtain the simulated results of the same.

APPARATUS REQUIRED:

1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or behavioural level).
4. Enter the Verilog code in Altera software using the steps given below.
5. Check the syntax and simulate the above verilog code using Altera and verify the
functionality of the circuit with its simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and
verify the functionality of the circuit.

THEORY
If the register has both shifts and parallel‐load capabilities, it is referred to as a universal shift
register. The block diagram symbol and the circuit diagram of a four‐bit universal shift
register that has all the capabilities just listed are shown in Fig. The circuit consists of four D
flip‐flops and four multiplexers. The four multiplexers have two common selection inputss1
and s0. Input 0 in each multiplexer is selected when s1s0 = 00, input 1 is selected whens1s0 =
01, and similarly for the other two inputs. When s1s0 = 00,the present value of the register is
applied to the D inputs of the flip‐flops. This condition forms a path from the output of each
flip‐flop into the input of the same flip‐flop, so that the output recirculates to the input in this
mode of operation. The next clock edge transfers into each flip‐flop the binary value it held
previously, and no change of state occurs.

43
PROGRAM

44
SIMULATED RESULTS

RESULT

45
46
 DESIGN, SIMULATION & IMPLEMENTATION OF
Exp. No. : 9 Date:
UP DOWN COUNTER
AIM:
To design and simulate a 4 bit up down counter in Altera ISE13.2 and obtain the waveforms.

APPARATUS REQUIRED:

1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or behavioural level).
4. Enter the Verilog code in Altera software using the steps given below.
5. Check the syntax and simulate the above verilog code using Altera and verify the
functionality of the circuit with its simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and
verify the functionality of the circuit.

THEORY:

Counters are used in many different applications. Some count up from zero and provide a
change in state of output upon reaching a predetermined value; others count down from a
preset value to zero to provide an output state change. However, some counters can operate in
both up and down count mode, depending on the state of an up/down count mode input pin.
They can be reversed at any point within their count sequence.

47
TRUTH TABLE:

PROGRAM

48
SIMULATED RESULTS:

RESULT:

49
50
 DESIGN, SIMULATION & IMPLEMENTATION OF
Exp. No. :10 Date:
STATE MACHINES

AIM:
To design, simulate and implement a Finite State Machine using verilog and to observe the
waveforms in Altera ISE13.2.

APPARATUS REQUIRED:
1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS

PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or
behavioural level).
4. Enter the Verilog code in Altera software using the steps given
below.
5. Check the syntax and simulate the above verilog code using Altera
and verify the functionality of the circuit with its
simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA
BOARDS and verify the functionality of the circuit.

Fig. 1: Moore State Machine

Fig. 2: Mealy State Machine

The logic in a state machine is described using a case statement or the equivalent (e.g., if-
else). All possible combinations of current state and inputs are enumerated, and the
appropriate values are specified for next state and the outputs. A state machine may be coded
as in Code 1 using two separate case statements, or, as in code 2, using only one. A single

51
case statement may be preferred for Mealy machines where the outputs depend on the state
transition rather than just the current state.
Consider the case of a circuit to detect a pair of 1's or 0's in the single bit input. That is, input
will be a series of one's and zero's. If two one's or two zero's comes one after another, output
should go high. Otherwise output should be low.
Here is a Moore type state transition diagram for the circuit. When reset, state goes to 00; If
input is 1, state will be 01 and if input is 0, state goes to 10. State will be 11 if input repeats.
After state 11, goes to 10 state or 01 depending on the inp, since overlapping pair should not
be considered. That is, if 111 comes, it should consider only one pair.

PROGRAM (MOORE STATE MACHINE):

52
SIMULATED RESULTS:

MEALY STATE MACHINE:

When reset, state becomes idle, that is 00. Next, if 1 comes, state becomes 01 and if 0 comes
state becomes 10 with output 0. We have showed input 1, output 0 as 1/0. If input bit repeats,
output becomes 1 and state goes to 00.

PROGRAM (MEALY STATE MACHINE):

53
SIMULATED RESULTS:

RESULT:

54
 DESIGN, SIMULATION &
Exp. No. :11 IMPLEMENTATION OF 4 x 4 RANDOM Date:
ACCESS MEMORY

AIM :
To design, simulate and implement the 64 x 4 Random Access Memory using Altera
ISE13.2 and obtain the simulated results of the same.

APPARATUS REQUIRED:

1. Personal Computer
2. ALTERA QUARTUS II
3. ALTERA -CYCLONE-II - FPGA BOARDS
PROCEDURE:

1. Draw the logic diagram for the given combinational circuit.

2. Write the truth table.
3. Write the Verilog code (Gate level or Data flow level or behavioural level).
4. Enter the Verilog code in Altera software using the steps given below.
5. Check the syntax and simulate the above verilog code using Altera and verify the
functionality of the circuit with its simulated output waveform.
6. Implement the logic gates using ALTERA -CYCLONE-II - FPGA BOARDS and
verify the functionality of the circuit.
Theory
A memory unit is a collection of storage cells, together with associated circuits needed to
transfer information into and out of a device. The architecture of memory is such that
information can be selectively retrieved from any of its internal locations. The time it takes to
transfer information to or from any desired random location is always the same—hence the
name random‐access memory, abbreviated RAM. In contrast, the time required to retrieve
information that is stored on magnetic tape depends on the location of the data. A memory
unit stores binary information in groups of bits called words. A word in memory is an entity
of bits that move in and out of storage as a unit.

55
 A memory word is a group of 1’s and 0’s and may represent a number, an instruction,
one or more alphanumeric characters, or any other binary‐coded information. A group of 8
bits is called a byte. Most computer memories use words that are multiples of 8 bits in length.
Thus, a 16‐bit word contains two bytes, and a 32‐bit word is made up of four bytes. The
capacity of a memory unit is usually stated as the total number of bytes that the unit can store.

Program

SIMULATIED RESULTS

RESULT

56
 TRANSISTOR LEVEL SIMULATION OF
Exp. No. :12 Date:
CMOS INVERTER

AIM:
To design a CMOS Inverter and to study the DC & Transient characteristics and to
measure the delay for 180nm technology using EDA tools.

APPARATUS REQUIRED:

• PC with NGSPICE, MAGIC VLSI, XCIRCUIT/E-SIM.

THEORY:

The inverter is the most fundamental logic gate that performs a Boolean operation on a
single input variable. Many of the basic principles employed in the design and analysis of
MOS inverters can be directly applied to more complex logic circuits, such as NAND and
NOR gates. CMOS Inverter consists of an enhancement-type nMOS transistor and an
enhancement type pMOS transistor, operating in complementary mode. The circuit topology
is complementary push-pull in the sense that for high input, the nMOS transistor drives (pulls
down) the output node while the pMOS transistor acts as the load, and for low input the
pMOS transistor drives (pulls up) the output node while the nMOS transistor acts as the load.

(1) DC Characteristics

Schematic:

57
Simulation Output Waveform:

(2) Transient Characteristics

Schematic:

Simulation Output Waveform:

58
RESULT:

59
60
 TRANSISTOR LEVEL SIMULATION OF
Exp. No. :13 Date:
DIFFERENTIAL AMPLIFIER

AIM:
To design and simulate a simple five transistor differential amplifier and to find gain and
CMRR.

APPARATUS REQUIRED:

• PC with NGSPICE, MAGIC VLSI, XCIRCUIT/E-SIM.

Differential amplifier with resistive load

61
OUTPUT WAVEFORM:

COMMON MODE DIFFERENTIAL AMPLIFIER:

3. Perform the same steps and calculate the (Vout/Vin) by following

analysis

Transient analysis waveform:

OUTPUT WAVEFORM:

62
 AC analysis waveform:

Differential amplifier with current mirror load

63
Transient analysis:

AC analysis waveform:

64
Current mirror load (Common mode):

Transient analysis:

65
 AC analysis:

RESULT:

66
 LAYOUT EXTRACTION OF CMOS
Exp. No. :14 INVERTER Date:

AIM:
• To perform automatic layout generation and extraction for CMOS Inverter using MAGIC
VLSI.
APPARATUS REQUIRED:
• PC with MAGIC VLSI.
PROCEDURE:
Introduction to MAGIC Part II: A Step-by-Step Layout Example of a CMOSInverter

The following is a step-by-step example of how to perform a VLSI layout of a basic CMOS logic
inverter as shown below in the following schematic diagram:

Start MAGIC from the UNIX prompt as described in by typing:

my_prompt> magic -T scna.60 inverter

Expand the resulting graphics window over a portion of the screen, but not so large that you cannot
see the text window prompt where commands are entered. Remember that the graphics window must
be active and the cursor must always point to the graphics window when entering commands. Zoom
out and activate the lambda grid so that it is easier to see what you are doing. Type:
:zoom 0.5 and :grid 1

The order in which layers are painted in the graphics window is not important, so the layout steps
described here are a recommended guideline as opposed to etched-in-stone rules. Since the device
channel width W and length L are specified, you can start by painting the device active areas first: p-
diffusion (brown) for the PMOS fet and n- diffusion (green) for the NMOS FET.

67
The PMOS transistor has a channel width of W=4.8um, which is equal to 8 lambda (i.e. (4.8/.6) in
our selected technology. The channel length L=1.2um equals 2 lambda using the same reasoning.
The design rules specify that we need at least 4 lambda for the source and drain contacts, plus at least
one lambda between the poly gate and the source/drain contacts. Using left and right mouse clicks,
shape a box 8 lambda wide and 2+4+4+1+1=12 lambda high. The command:
:paint pdiff

paints the PMOS active area (p-diffusion) in this area. The NMOS transistor has the channel width
W=1.8um, which is equal to 3 lambda, and the channel length L=1.2um (2 lambda). Make a 3
lambda (width) by 12 lambda (height) box under the p-diffusion area painted in the previous step.
You may want to align the left edge of the box with the left edge of the p-diffusion area. The
command:
:paint ndiff

paints the metal1 (Vdd!) wire in your area (see Figure 4). Next, select the Vdd! wirewith the s macro,
position the cursor to the lower left corner aligned with the left edge of the Vdd! wire and the bottom
edge of the n-diffusion area, and type c. This will copy the metal1 wire to where the GND! wire
should be.

Initial Layout

To make a contact between the Vdd! wire and pdiffusion area, form a box over at the overlap
between the metal1 and pdiffusion areas and type the command:
:paint pdc

to make a contact between the GND wire and ndiffusion (source of the NMOS), make a box over
the overlap between metal1 and n-diffusion layers. Type the command:
:paint ndc

Note that design rules specify that the minimum contact area is 4 lambda by 4 lambda. At this point,
your layout should look like Figure 4 below:

68
 Inverter Layout with metal1added

The next step is to paint the n-well area where the PMOS fet is located. Similarly for NMOS
devices a p-well area should be added, although this step is not 100% necessary since MAGIC
knows already that a p-well area is needed (assuming the technology process is n-well based)3.
Nevertheless, it remains good practice to place the p-well layer by hand.

To paint the n-well region place a box extending at least 5 lambda above and below the pdiffusion
area and as wide as the metal1 wires. The command:
:paint nwell

paints the n-well for the PMOS fet. At this point, we can also add contacts between the GND! wire
and the p-substrate (body of the NMOS fet), as well as between the Vdd! wire and the n-well (body
of the PMOS fet). Place a 4-lambda by 4-lambda box over the metal1 wire, but do not overlap the
PMOS source contact you already made. The command:
:paint nnc

paints an n-well area to the metal1 contact. If the contact is too close to the pdiffusion-to-metal1
contact, white dots will appear. Select the n-well-to-metal1 contact you just created and use the Q or
R macros to move it away until the white dots disappear. Repeat the same to create a metal1
(GND!) to p-substrate contact. Type:
:paint ppc

The layout should now look like the paint in Figure below.

69
 Addition of nwell to CMOSinverter.

The body contacts (such as the ones you just created) should always be located as close as possible to
the device source contacts to minimize the possibility of latch-up that plagues CMOS circuits. It is
also a good practice to put as many body contacts as possible when space permits.

The next step is to make the fet drain contacts. To connect the drains of the NMOS and the PMOS
transistors, paint an output node using metal1. Use the same procedure of steps that you used to
create the Vdd!, GND! wires, and source contacts. Note that the simplest way to apply paint in a box
is to click the middle-mousebutton over an area already painted with the desired layer in your design.
This faster method was previously omitted intentionally, so that necessary experience would be
gained in entering and executing MAGIC commands, and the fact that entering paint layers like this
may not be the best method in all cases.

You should now have a layout that looks approximately like Figure 6 on the next page.

The next step is to paint and connect the gates of the NMOS and the PMOS fets. Position a 2-lambda
wide horizontal box to overlap the middle n-diffusion area by at least 2-lambda on both sides. Type
the commands:
:paint poly

Notice how the area of poly-to-ndiffusion overlap changes to an area with green/red stripes. This is
the channel of the NMOS fet. Create a similar poly box over the p- diffusion area. Correct the size or
position of the poly areas if you have white dots indicating design rule violations. Connect the poly
areas and make the input node. The current layout should look like Figure 7 on the next page.

The final step is to put labels on the important signal nodes. Execute a left-click / right-click on the
poly area, close to the left edge. You should see a small yellow "+" exactly at that spot. To label the
"+", type:
:label in

70
which effectively labels the poly shown as the input node of the inverter. Similarly, label the Vdd!
and GND! wires as Vdd! and GND!, respectively, and the output wire/terminal as "out".

Inverter with output section added.

Inverter with poly section added

The final layout should appear as in Figure as shown below

71
 Completed Layout

The grid has been turned off using the g macro, and the circuit diagram is shown again for
easy comparison with the layout.

Now, save the layout that you created with the command:
:save

Extract the layout to create the output file that will be used with a simulator by typing:
:extract

And finally, exit MAGIC by typing:

:quit

72
RESULT:

73
74
 EXPERIMENT BEYOND THE SYLLABUS

Exp. No. :15

DOMINO LOGIC CIRCUIT SIMULATION Date:

AIM:

To design and simulate combinational circuit using the Schematic entry tool and to
obtain its characteristics.

APPARATUS REQUIRED:
• PC with NGSPICE, MAGIC VLSI, XCIRCUIT/E-SIM

THEORY:
The dynamic static pair together is called domino logic. During pre charge the output of
the dynamic gate is ‘1’ and the output of the inverter is ‘0’. During evaluation, the output of the
dynamic gate id charged or discharged depending on inputs. This affects the second gate output
and this will ripple through the whole chain one after the other, similar to a line of falling
dominoes. Hence the name domino logic.
DOMINO INVERTER:

SIMULATED OUTPUT:

75
DOMINO NAND:

SIMULATED OUTPUT:

RESULT:

76
77