19ECE304 – Microcontrollers and

Interfacing (3 0 3 4)

Mr. Giriraja C V
Ms. Jayashree M Oli
Ms. Priya B K

1
Chapter 3 – ARM Assembly Language Programming
Chapter 5 – The ARM Instruction set- 5.1 to 5.15, 5.20, 5.22, 5.23

Instruction Set:
• Two instruction sets
• ARM
• Standard 32-bit instruction set
• THUMB
• 16-bit compressed form
• Code density better than most CISC
• Dynamic decompression in pipeline

2
ARM Instruction Set:
• Features:
• Load/Store architecture
• 3-address data processing instructions
• Conditional execution
• Load/Store multiple registers
• Shift & ALU operation in single clock cycle

4
ARM Instruction Set: ARM Instruction Set

Data processing
instructions

Data transfer
instructions
Block transfer
instructions

Control flow instructions

Multiply instructions
Software interrupt
instructions 5
Data types:
• Supports six data types:
1. 8 bit signed and unsigned bytes
2. 16 bit signed and unsigned half words, aligned on 2 byte boundaries
3. 32 bit signed and unsigned words, aligned on 4 byte boundaries
• ARM instructions are 32 bit word and aligned on 4 byte boundaries
• Thumb instructions are 16 bit half word and aligned on 2 byte boundaries
• Operands are 32 bit
• Shorter data types are supported by data transfer instructions
• When byte is loaded from memory, it is zero or sign extended to 32 bits and treated as a 32 bit
value for internal processing
• ARM coprocessor supports floating point values

6
Data Processing Instructions:
• Arithmetic and logical operations
• Modifies the data values
• 3-address format – for ex: ADD R1, R2, R3
• Two 32-bit operands
(operand 1 is register, operand 2 is register or immediate data (literals) or a shifted register)
• 32-bit result placed in a register
• Barrel shifter for operand 2 allows full 32-bit shift within the instruction cycle
• Each operand register and result register is independently specified in the instruction
• Data can be unsigned integer or signed 2’s complement integer
• Shift applied can be arithmetic or logical or rotate
• C flag is set for addition, subtraction and compare instruction
• None of the three register should be PC except for shift operation
• If PC is used as a source, the value given is the address of the current instruction + 8 bytes
• PC can
7
be destination register if it is a branch instruction
Data Processing Instructions:
• Arithmetic operations
• ADD, ADC, SUB, SBC, RSB, RSC
• Bit-wise logical operations
• AND, EOR, ORR, BIC
• Register movement operations
• MOV, MVN
• Comparison operations
• TST, TEQ, CMP, CMN

8
Arithmetic Operations:
• Performs binary
arithmetic on
two 32 bit
operands

• Operands may
be unsigned or
2’s complement
signed integer

• C bit in CPSR
is effected

9
Subtraction:
Bit wise logical operations:
• Performs Boolean
logic operation on
each bit pair of the
input operands
Register movement operation:
Compare operations:

• If R1 > R2, then C=1

• If R1 < R2, then C=0
• Second operand is inverted and
performs subtraction
• Used for negative numbers

• Used to test the flags

16
17
18
5) Base plus offset addressing mode

19
Conditional execution of instruction:
29
Shifted Register operands:

• LSL- Logically shift left by the

specified number of bits and fill the
vacated bits at the LSB with zeros
• Second register operand is a shift
operation before it is combined with
first operand
• Single clock cycle execution
• LSR- Logically shift right by the
specified number of bits and fill
the vacated bits at the MSB with
zeros

• ASR- Logically shift right by the

specified number of bits and fill
the vacated bits at the MSB with
zeros if source operand is positive
else with ones if negative
• ROR – Rotate towards right by the
specified number of bits and the
shifted bits at the LSB are used to
fill the vacated bits at the MSB in
the same order as well as carry flag.

• RRX- Rotate right by one place

and bit 31 is filled with the value
of Carry flag and bit 0 moves to
Carry flag
• Example for 4 address format instruction
Setting the condition codes:
• Comparison operation sets the condition codes
• Data processing operation sets the condition codes
• It is performed by adding the letter S to the instruction and S stands for SET condition
codes
• Used to control the program flow through conditional branch instruction
• For example addition of two 64 bit numbers shown below.

35
Multiply Instructions:
• Special form of data processing instruction
• Integer multiplication (32-bit result)
• Long integer multiplication (64-bit result)
• Built in Multiply Accumulate Unit (MAC)
• Multiply and accumulate instructions add product to running total

• Over flag is preserved 36

Multiply Instructions:
MUL Multiply 32-bit result

MLA Multiply accumulate 32-bit result

UMULL Unsigned multiply 64-bit result

UMLAL Unsigned multiply accumulate 64-bit result

SMULL Signed multiply 64-bit result

SMLAL Signed multiply accumulate 64-bit result

37
38
43
44
Data Processing Instructions:
Conditional codes
e.g.:
+
Data processing instructions if (z==1) R1=R2+(R3*4)
+ compiles to
Barrel shifter
EQADDS R1,R2,R3, LSL #2
=
( SINGLE INSTRUCTION ! )
Powerful tools for efficient coded programs

45
Data Transfer Instructions:
• Moves data between register and memory

• Three basic forms

1. Single register load and store instruction
2. Multiple register load and store instruction
3. Single register swap instruction

46
Data Transfer Instructions:
Single register load and store instructions
• Load/store instructions
• Flexible
• Used to move signed and unsigned Word, Half Word and Byte to and from registers
• Can be used to load PC (if target address is beyond branch instruction range)

LDR Load Word STR Store Word

LDRH Load Half Word STRH Store Half Word

LDRSH Load Signed Half Word STRSH Store Signed Half Word

LDRB Load Byte STRB Store Byte

LDRSB Load Signed Byte STRSB Store Signed Byte

47
Single word and unsigned byte data transfer LDR/STR, LDRB/STRB:
• Flexible way to transfer single bytes or words between register and memory
• Uses load store instructions
• Immediate, register offset, auto –indexing and PC relative addressing modes can be used
Note:
• If PC is used as the base address, it delivers the address of the instruction +8 bytes.
For ex: LDR R1, [PC]
• PC should not be used as offset register nor with any auto-indexing or post-indexing mode.
For ex: LDR R1, [R0, PC]! and LDR R1,[R0], PC both are invalid
• Loading a byte into PC should be avoided. For ex: LDRB PC, [R0]
• Storing PC content to memory to be avoided. For ex: STR PC, [R0]
• When word is loaded from a non-word-aligned address, the loaded data is the word – aligned
word, word containing the addresses byte, rotated so that addresses byte is in the LSB of the
destination register. For ex: LDR R0,=0x40000001, LDR R1, [R0]
• When word is stored to a non-word-aligned address, the bottom two bits of the address are
ignored and the word is stored as though it is zero. For ex: LDR R0,=0x40000001, STR R1,
[R0]
Half-word and signed byte data transfer instructions:
• S and H bits define the type of the operand to be transferred
• Load signed-byte (LDRSB), signed half-word (LDRSH) or unsigned half-word (LDRH)
• Store half-word (STRH)
Register indirect addressing:
• Base-plus-offset and offset can be maximum of 4K bytes may be added or subtracted with
the base address
• Base-plus-index addressing
• Base register contains address
• Offset can be a register or immediate data
Block Transfer Instructions or multiple register load and store
instructions
• Load/Store Multiple instructions (LDM/STM)
• Less flexible
• Large amount of data is transferred efficiently
• Whole register bank or a subset copied to memory or restored with single instruction
Mi
• Used for procedure entry and exit LDM
Mi+1
• Used to save and restore workspace register R0
Mi+2
• Used for high bandwidth memory block copy routines R1
• Base register is word aligned R2
Mi+14
• { } – block transfer
Mi+15
• Registers are in increasing order only R14 STM
• It operates at 4 times faster than single load store instructions R15
52
• But complex in nature and cannot be executed in single clock cycle
• Used by the operating system to load or store the user-mode registers to save or restore the
user process state
• Used to restore CPSR from SPSR
Stack addressing:
• Stack is based on LIFO form
• Dynamic memory allocation, used in recursive function
• It is a linear data structure which grows in increasing or decreasing order
• Stack pointer holds the current address of the stack and always points to the top of the stack
• Stack can be
1. Full stack
2. Empty stack
Stack can be
1. Full ascending- Stack grows up in increasing memory address and base register points to the highest
address contains a valid data
2. Full descending- Stack grows down in decreasing memory address and base register points to the
lowest address contains a valid data
3. Empty ascending- Stack grows up in increasing memory address and base register points to the first
empty location above the stack
4. Empty descending- Stack grows down in decreasing memory address and base register points to the
70
first empty location below the stack
Single register Swap Instruction:
• Exchanges a word between registers R0
• Between register and memory is exchanged
R1
• Less used in user level program
R2
• Two cycles but single atomic action
• Support for RT semaphores
• SWP{cond}{B} Rd, Rm, [Rn]
{B} if B is present then byte transfer, otherwise word transfer R7
• Rd, Rm, Rn are expressions evaluating to valid register numbers R8
• SWP R0, R1, [R2] ; Load R0 with the word addressed by R2 and store
R1 at R2.
• SWPB R2, R3, [R4] ; Load R2 with the byte addressed by R4, and
store bits 0 to 7 of R3 at R4. R15
• SWPEQ R0, R0, [R1] ; Conditionally swap the contents of the word
addressed by R1 with R0.
• PC should not be used with this instruction 76
• Base register should not be same as source or destination register
Control flow instructions:
• Neither processes the data nor moves it
• Used to cause a switch in the sequence of instruction execution
Branching Instructions can be
Unconditional and Conditional branch instructions
• Branch (B): Jumps forwards/backwards up to 32 MB
• Branch link (BL): Jumps + saves (PC+4) in LR
• Suitable for function call/return
• Condition codes for conditional branch instructions
• Branch exchange (BX) and Branch link exchange (BLX): same as B/BL +exchange
instruction set (ARM  THUMB)
• Only way to swap sets
77
 ARM Branches and Subroutines:
• B <label>
• PC relative. ±32 Mbyte range.
• BL <subroutine>
• Stores return address in LR
• Returning implemented by restoring the PC from LR
• For non-leaf functions, LR will have to be stacked
• Leaf subroutine- Subroutine does not call another subroutine
func1 func2
STMFD :
sp!,{regs,lr} :
:
: :
:
BL func2 :
BL func1
: :
:
LDMFD MOV pc, lr
: sp!,{regs,pc}
83
Branch exchange (BX), branch with link and exchange (BLX):
• Used to switch the sequence of execution of program
• Used to switch to Thumb (16-bit) instruction set and for returning symmetrically to ARM and
Thumb calling routines
• BLX is available only on ARM processors that support architecture v5T
• The branch target is specified in a register Rm.
• Bit [0] of Rm is copied into the T bit in the CPSR and bits[31:1] are moved into the PC
• If Rm [0] is 1, the processor switches to execute Thumb instructions and begins executing at
the address in Rm aligned to a half-word boundary by clearing the bottom bit.
• If Rm [0] is 0, the processor continues executing ARM instructions and begins executing at
the address in Rm aligned to a word boundary by clearing Rm[l].
BLX Label:
• Branch target is an address computed by sign extending the 24-bit offset specified in the
instruction, shifting it left two places to form a word offset, then adding it to the program
counter which contains the address of the BX instruction plus eight bytes.
• The H bit (bit24) is also added into bit 1 of the resulting address, allowing an odd half-word
address to be selected for the target instruction which will always be a Thumb instruction (BL
is used to target an ARM instruction).
• The range of the branch instruction is +/-32 M bytes.
• B{L}X{<cond>} Rm
• BLX <target address>
Supervisor calls:
• Supervisor is a program which operates at privileged level
• Can access system resources
• Software Interrupt instruction also known as supervisor call
• SWI instruction
• Forces CPU into supervisor mode and begins executing the instruction from the address
0x08
• Usage: SWI #n
31 28 27 24 23 0

Cond Opcode Ordinal

 Maximum 224 calls

 Suitable for running privileged code and making OS calls
91
• If the condition is passed the instruction enters supervisor mode using the standard ARM
exception entry sequence.
1. Save the address of the instruction after the SWI in r14_svc.
2.Save the CPSR in SPSR_svc (Supervisor Calls (SVC)).
3.Enter supervisor mode and disable IRQs (but not FIQs) by setting CPSR[4:0] to 100112 and
CPSR [7] to l.
4.Set the PC to 08(16) and begin executing the instructions there.
• To return to the instruction after the SWI the system routine must not only copy r14_svc back
into the PC, but it must also restore the CPSR from SPSR_svc
Note:
• SWI is executed even if processor is already in supervisor mode but R14_svc and SPSR_svc
has to be saved else these registers are overwritten
• The first instruction at 08(16) is a branch to the SWI handler

92
95
Breakpoint instruction (BKPT) V5T only):
• Used for software debugging
• Processor will break from normal instruction execution and enters debugging
• Leads to pre fetch abort
• BRK
• Unconditional instructions
Count leading zeros (CLZ -architecture v5T only):
• Used to renormalize the numbers
• The instruction sets Rd to the number of the bit position of the most significant 1 in Rm.
• If Rm is zero Rd will be set to 32.
Privileged modes:
• Used to handle
1. Exceptions
2. Supervisor calls
3. Software interrupts
• Privileged mode is entered through controlled mechanism
• Using memory protection, privileged modes allow a fully protected operating system to be
built
• Used for trapping errant software
• Current operating mode is defined by the bottom five bits of CPSR

100
SPSR- Saved Program Status Register:
• All privileged mode except system mode is associated with SPSR
• Used to save the state of CPSR when any privileged mode is entered
• Once it is returned from privileged mode, SPSR is restored back to CPSR
• If privileged mode is used as a re-entrant then SPSR must be copied to general register

103
Exception:
• Used to handle unexpected events which arise during the execution of program such as
• Interrupt
• Memory fault
• Software interrupt
• Undefined instruction traps
• System reset function
It is divided into three groups
1. Exception generated as the direct effect of executing an instruction
Ex: Software interrupt, undefined instruction, pre fetch abort
2. Exception generated as the side effect of executing an instruction
Ex: data abort, memory fault
3. Exception generated externally unrelated to the instruction flow
Ex: Reset, IRQ, FIQ 104
Exception entry:
• When exception occurs, ARM completes the execution of the current instruction and check
whether it is due to side effect or due to external event or direct effect
• Processor changes the operating mode to the particular exception
• Saves the address of the next instruction in R14
• Saves the value of CPSR in SPSR_mode of the exception mode
• Disables IRQ by making bit7 of CPSR as 1
• If exception is FIQ then bit 6 of CPSR is set to 1
• PC starts executing the exception from the relevant vector address
• Vector address contains a branch to the routine
• Registers in privileged modes are used to hold the return address
• Stack pointer is used to save user register contents and can be used by the exception handler

105
Exception return:
• Once the exception has been handled the user task is normally resumed.
• This requires the handler code to restore the user state exactly as it was when the exception
first arose
• Any modified user registers must be restored from the handler's stack.
• The CPSR must be restored from the appropriate SPSR.
• The PC must be changed back to the relevant instruction address in the user instruction
stream.
• The last two steps cannot be carried out independently
• For ex:
• If CPSR is restored first, R14 holding the return address is no longer accessible
• If PC is restored first exception handler loses control of instruction stream and CPSR cannot
be restored first

106
Exception return:
• ARM provides two mechanism to make both the steps
1. Used when return address is stored in R14
2. Used when return address is stored on to a stack

Used when return address is stored in R14:

• To return from a SWI or undefined instruction trap use:
• MOVS pc, r14
• To return from an IRQ, FIQ or pre fetch abort use:
• SUBS pc, r14, #4
• To return from a data abort to retry the data access use:
• SUBS pc, r14, #8

107
Exception return:
• IRQ and FIQ must return one instruction early in order to execute the instruction that was
'usurped' for the exception entry
• Pre fetch abort must return one instruction early to execute the instruction that had caused a
memory fault when first requested
• Data abort must return two instructions early to retry the data transfer instruction that was the
instruction before the one 'usurped' for the exception entry

Used when return address is stored on to a stack:

• LDMFD R13!, { R0-R3,PC}^
• ^ - Special form of instruction

108
Exception priorities:
1. Reset (highest priority)
2. Data abort
3. FIQ
4. IRQ
5. Pre fetch abort
6. SWI, undefined instruction (including absent coprocessor)
• If FIQ, IRQ and other exception other than reset occurs simultaneously, FIQ will get chance
due to highest priority
• But if third one is data abort then data abort will get chance and then FIQ will get chance

109
Status register to general register transfer instructions:
• To save or modify the contents of the CPSR or the SPSR of the current mode, those
contents must first be transferred into a general register, the selected bits modified and then
the value returned to the status register.
• MRS{<cond>} Rd, CPSR
• MRS r0, CPSR ; move the CPSR to r0
• MRS r3, SPSR ; move the SPSR to r3
• SPSR should not be used in user or system mode
General register to status register transfer instructions:
• To save or modify the contents of the CPSR or the SPSR of the current mode, those contents
must first be transferred into a general register, the selected bits modified and then the value
returned to the status register.
• MSR{<cond>} CPSR_f or SPSR_f, #<32-bit immediate>

• MSR{<cond>} CPSR_< field > or SPSR_<field>, Rm

where <field> is one of:

• c -the control field -PSR[7:0].
• x -the extension field -PSR[15:8] (unused on current ARMs).
• s -the status field -PSR[23:16] (unused on current ARMs).
• f- the flags field -PSR[31:24].
General register to status register transfer instructions:
To set the N, Z, C and V flags:
• MSR CPSR_f, # 0xf0000000; set all the flags

To set just the C flag, preserving N, Z and V:

• MRS r0, CPSR; move the CPSR to r0
• ORR r0, r0, # 0x20000000; set bit 29 of r0
• MSR CPSR_f, r0; move back to CPSR

To switch from supervisor mode into IRQ mode (for instance, to initialize the IRQ stack
pointer at start up):
• MRS r0, CPSR ; move the CPSR to r0
• BIC r0, r0, #0xlf ; clear the bottom 5 bits
• ORR r0, r0, #0x12 ; set the bits to IRQ mode
• MSR CPSR_f, r0 ; move back to CPSR
Note:
• Attempt to modify CPSR [23:0] in user mode have no effect
• Attempt to access SPSR [23:0] in user mode or system mode should be avoided
Memory faults:
Page absent:
• Addressed memory location has been paged out to disk
• Infrequently used pages are held on disk, attempt to access instruction or data from such a
page will fail
• System software identifies the cause and fetch the page from disk to memory
• But fetching a page from disk is a slow process
Page protected:
• Memory location is temporarily inaccessible
• When a page is loaded into memory, OS may make it initially read only
• When an attempt is made to write results in fault
Soft memory errors:
• Due to alpha particles radiation change, changing the state of a dynamic RAM storage cell
• Hardware error detector detects and forwards to software error corrector which corrects the
error
Memory faults:
Pre fetch abort:
• During instruction fetch
• Internally ARM puts the instruction to the pipeline along with abort flag
• Once the instruction enters the decode stage, decoder on seeing the flag generates the pre
fetch abort vector
Data abort:
• During accessing data from memory
Abort timing:
• When memory fault occurs, it need to preserve the state
ARM data aborts:
• PC is preserved and stored to R14_abt
115