MTH1235 Applied Activity 2 Yousef Elarian Design and Schema drawing of

Logic Circuits
Within groups of up to 4 students, perform the following tasks:
Task 1. [15 points] Design a logic circuit for an encoder:

1) Complete the truth table for a 4x2 encoder

D0 D1 D2 D3 y z
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1

2) Write the Boolean expressions for y and z from the truth table

y = D2 + D3

z = D1 + D3

3) Draw the corresponding circuit diagram using OR gates only

2. [30 points] Design a logic circuit for a decoder:

1) Complete the truth table for a 2x4 decoder

y z D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

2) Write the Boolean expressions for each of the four outputs from the truth table
 MTH1235 Applied Activity 2 Yousef Elarian

Design and Schema drawing of Logic Circuits

Task
D0 = y’. z’

D1 = y’. z

D2 = y. z’

D3 = y. z

3) Draw the circuit for the decoder above using NOT and AND gates for inputs y and z

4) Complete the truth table for a 3x8 decoder

 MTH1235 Applied Activity 2 Yousef Elarian Design and Schema drawing of
Logic Circuits
x y z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

5) Write the Boolean expressions for each of the 8 outputs from the truth table
D0 = x’ y’ z’
D1 = x’ y’ z
D2 = x’ y z’
D3 = x’ y z
D4 = x y’ z’
D5 = x y’ z
D6 = x y z’
D7 = x y z
 MTH1235 Applied Activity 2 Yousef Elarian

Design and Schema drawing of Logic Circuits

Task
6) Draw the corresponding circuit diagram using AND gates only connecting x, x’, y, y’, z,
or z’
MTH1235 Applied Activity 2 Yousef Elarian Design and Schema drawing of
Logic Circuits
MTH1235 Applied Activity 2 Yousef Elarian

Design and Schema drawing of Logic Circuits

Task

3. [15 points] Multiplexer design:

1) Write the Sum of Products expression for the following 4x1 multiplexer

Y=S1’S0’I0+S1’S0I1+S1S0’I2+S1S0I3

2) The following is the block diagram of a 2x1 MUX.

Based on your understanding of it, draw the block diagram of a 4x1 multiplexer
MTH1235 Applied Activity 2 Yousef Elarian Design and Schema drawing of
Logic Circuits

3) The following is the circuit diagram of a 2x1 MUX. Complete the corresponding truth
table for Inputs S, I0, I1 and Output Y
S I1 I0 Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1
MTH1235 Applied Activity 2 Yousef Elarian

Design and Schema drawing of Logic Circuits

Task

4. [15 points] Design a logic circuit for a Full Adder (3 bits adder):

1) Complete the truth table for adding x, y, and z into Sum and Carry
x y z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

2) Write the full SoP expressions for S and C from the truth table without reduction

S= x⊕y⊕z

C = xy + yz + xz

3) Draw the corresponding circuit diagram of the full SoP using Inputs x’, x, y’, y, z’, z
Task 5. [25 points] Design a parity generator logic circuit
MTH1235 Applied Activity 2 Yousef Elarian Design and Schema drawing of
Logic Circuits
1) Write the truth table that takes a string of 4 bits, S3S2S1S0, and returns P which
equals 1 if the number of ones in it is EVEN in the string and 0 otherwise.
S3 S2 S1 S0 P
0 0 0 0 1

0 0 0 1 0

0 0 1 0 0
0 0 1 1 1

0 1 0 0 0
0 1 0 1 1
0 1 1 0 1

0 1 1 1 0

1 0 0 0 0
1 0 0 1 1

1 0 1 0 1

1 0 1 1 0
1 1 0 0 1

1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

2) Write the SoP expression for P from the truth table above without reduction

P = (S3'S2'S1'S0) + (S3'S2S1S0) + (S3S2'S1S0) + (S3S2S1'S0) + (S3S2S1S0)

MTH1235 Applied Activity 2 Yousef Elarian Design and Schema drawing of
Logic Circuits
3) Explain how we can convert this circuit into an Even-Parity generator for a string
of 4 bits by only adding one extra gate?

4) Write the truth table that takes a string of 3 bits, S2S1S0, and generates 1 if the
number of ones in it is even and zero otherwise

5) Write the SoP expression for P from the truth table above without reduction.

Upon the completion of your assignment, each group must select one member only to
submit a PDF document of the solution on behalf of all group members. Make sure to
include all group members' names and A-Numbers. You may type or handwrite and
scan your answers and their steps. Include enough snapshots if/whenever your group
makes use of any software tools.
Each group must work in isolation from other groups. Similarities between group
submissions (including similar mistakes) will be investigated and can result in academic
dishonesty charges, including a grade of zero and reporting to the college.