CSE3117-Microprocessors and

Microcontrollers

Lecture 1: Introduction

Prof. Dr. Shamim Akhter,

Computer Science and Engineering(CSE),
Ahsanullah University Science and Technology (AUST)
 Historical Background
Year Technology Feature
Vacuum Tube Bulky, Consume lots of power, unreliable
(@larger systems, one failed every couple of
hours or so)

1947 Transistor Solid State Circuit-Semiconductor Electronics

1959 Integrated Circuit
1965 Moore’s Law Cramming more components onto IC
 Today:
232 Transistors
Moore’s Law - 1965

@ Gordon E. Moore, “Cramming More Components onto

Integrated Circuits,” Electronics, pp. 114–117, April 19, 1965.
…
1975
1966
1965

…
64
32

216
double every year.
Component density
 Microprocessor and Microcontroller
µC CPU/µP

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control ALU I
Unit
CPU 300MHz I/O ports Registers N
8, 16 or 32 bits T
RAM-256KB Timer/Counter E
Control R
ROM System BUS Unit F
Timing Serial port/ Serial µP Timing A
Interface 32/64 bits C
4 GHz E
 Revisited: Component density double in every 18 months

@ Patterson, David A., Computer organization and design-3rd ed.

 Historical Background (Cont’d)
Year Technology Feature
Vacuum Tube Bulky, Consume lots of power, unreliable

1947 Transistor Solid State Circuit

1959 Integrated Circuit

1965 Moore’s Law Cramming more components onto IC

1961-65 Small Scale Integrated Circuit 10-100 transistors

Logic gates, FF, Latch
1966-70 Medium Scale Integrated Circuit Counter, MUX, Adder, ALU

1971 First Micro-processor Intel 4004, 4-bit µP

CPU-on a Chip
1976 First Micro-computer/controller Intel 8048
CPU, RAM, ROM BUS..etc
Computer-on a chip
1980-84 Very Large Scale Integrated Circuit 20k- 50 k transistors
DSP, RISC, 16/32 bit µP
2005 Ultra Large Scale Integrated Circuit 750k transistor
64 bit µP
 µP Evaluation

Embedded System /µC

• 4004-4bits
µP

• 4040

SP
• 8045 • DSP 2920
• 8008 • 8051 • Communication
• 8080-8bits • 8086 processor

Lower power Consumption,

• 8085 Micro Size, Micro Cost, • Intel IXP750
CISC • 8086-16bits, 1MB • Switches
• 8088 Higher Reliability, • Router
Versatility
• 80286-16bits, 16MB
• 80386-32 bits,4G M
• 80486
• Pentium (P5)
Washing Machine
• RISC
Toys, Digital
• Itanium (P7) Camera, Robots
Medical Equipment
Answering machine
8bits->16bits->32bits->64bits Fax, Printers
Pipelining, Super scaling, hyper threading, cache
Server, Desktop PC, Laptop etc
Memory system 8086 – Core 2
RAM
 Scalar vs. Vector Processors
Scalar processors: execute instruction that manipulate one (two) data item(s) at a
time. SISD-Single Instruction and Single Data

Instructions are decoded by the Control Unit and

then the Control Unit sends the instructions to
the processing units for execution.

Data Stream flows between the processors and

memory bi-directionally.

Examples: Older generation computers,

minicomputers, and workstations.

• Instructions are executed sequentially, and the system may or may not have
internal parallel processing capabilities.

• Parallel processing can be achieved by means of multiple functional units or by

pipeline processing.
Scalar vs. Vector Processors

Control Data Corporation

STAR-100 and Texas
Instruments Advanced
Scientific Computer (ASC),
which were introduced in
1974 and 1972, respectively.
GPU-Graphics Processing Unit

SIMD-Single Instruction and Multiple Data

Scalar vs Vector Processors
 Pipeline vs. Super Pipeline vs. Super Scale

Pipelined processors: performs one pipeline

stage at a clock cycle.

Superpipelined processors: Two pipeline stages

at a clock cycle. More than one instruction can
be in the pipeline at the same time and increase
the level of parallelism.
The functions performed in each stage can be split
into two nonoverlapping parts and each can
execute in half a clock cycle.

Superscalar processors: maintain parallel

pipeline and perform one pipeline stage at one
clock cycle. Manipulates multiple functional
units where one data processes in one
Functional unit FU (Example ALU…) as well.

Improve the performance of the execution of scalar

instructions
 Effect of Dependency
@Superscaler Processor
https://www.youtube.com/watch?v=VcoVYfDVEww
Multicore and Hyper Threading
 Advances in Processor Micro architecture

Solve the problem of dependencies

Intel Pentium Pro (1995),
introduced in the pipelined superscalar MIPS R10000 (1996),
processor.

20 stages

https://ac.els-cdn.com/S2090447915001380/1-s2.0-S2090447915001380-main.pdf?_tid=794c7d69-c2a8-4c65-8db6-
bf654b6f0495&acdnat=1525703493_5ac68bd71d10b8863e5e7c098cf1db3d
 In Order Vs Out of Order Processor
1. Instruction fetch. 1. Instruction fetch.

2. Instruction dispatch to an instruction

queue (also called instruction buffer
2. If input operands are available (in
or reservation stations).
processor registers, for instance),
the instruction is dispatched to the 3. The instruction waits in the queue
appropriate functional unit. until its input operands are available.
3. If one or more operands are during The instruction can leave the queue
the current clock cycle (generally before older instructions.
because they are being fetched
memory), the processor until they 4. The instruction is issued to the
are available. appropriate functional unit and
3. The instruction is executed by the executed by that unit.
appropriate functional unit. 5. The results are queued.
4. The functional unit writes the 6. Only after all older instructions have
results back to the register file. their results written back to the
register file, then this result written
back to the register file. This is
called the graduation or retirement
stage.
Multicore vs Multiprocessors
• Chapter 1-1