전자회로 Floyd 10판 솔루션 찐
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Chapter 1
Introduction to Semiconductors
Section 1-1 The Atom
1. Atoms have a planetary type of structure that consists of a central nucleus surrounded by
orbiting electrons. The nucleus consists of positively charged particles called protons
and uncharged particles called neutrons.
2. A shell is an energy level in which the orbits of electrons are grouped.
3. An atom with an atomic number of 6 has 6 electrons and 6 protons.
4. The third shell of an atom can have 2n2 2(3)2 18 electrons.
Section 1-2 Materials Used in Electronics
5. The materials represented in Figure 121 in the textbook are
(a) insulator (b) semiconductor (c) conductor
6. An atom with four valence electrons is a semiconductor.
7. In a silicon crystal, each atom forms four covalent bonds.
Section 1-3 Current in Semiconductors
8. When heat is added to silicon, more free electrons and holes are produced.
9. Current is produced in silicon at the conduction band and the valence band.
10. The conduction band is not part of the crystal structure, so there are no holes.
11. The valence electrons are attracted to the positive ions, keeping the positive ions together
and forming the metallic bond.
Section 1-4 N-Type and P-Type Semiconductors
12. Doping is the carefully controlled addition of trivalent or pentavalent atoms to pure
(intrinsic) semiconductor material for the purpose of increasing the number of majority
carriers (free electrons or holes).
13. Antimony is a pentavalent (donor) material used for doping to increase free electrons.
Boron is a trivalent (acceptor) material used for doping to increase the holes.
Chapter 1
Section 1-5 The PN Junction
14. The electric field across the pn junction of a diode is created by donor atoms in the n
region losing free electrons to acceptor atoms in the p region. This creates positive ions in
the n region near the junction and negative ions in the p region near the junction. A field
is then established between the ions.
15. The barrier potential of a diode represents an energy gradient that must be overcome by
conduction electrons and produces a voltage drop, not a source of energy.
Chapter 2
Diodes and Applications
Section 2-1 Diode Operation
1. To forward-bias a diode, the positive terminal of a voltage source must be connected to
the p region.
2. A series resistor is needed to limit the current through a forward-biased diode to a value
that will not damage the diode because the diode itself has very little resistance.
3. Reverse-bias voltage up to the breakdown value can be applied.
4. The high reverse-bias voltage imparts energy to the free minority electrons so that as they
speed through the p region, they collide with atoms with enough energy to knock valence
electrons out of orbit and into the conduction band. The newly created conduction
electrons are also high in energy and repeat the process. If one electron knocks only two
others out of their valence orbit during its travel through the p region, the numbers
quickly multiply. As these high-energy electrons go through the depletion region, they
have enough energy to go through the n region as conduction electrons, rather than
combining with holes.
Section 2-2 Voltage-Current Characteristic of a Diode
5. To generate the forward bias portion of the characteristic curve, connect a voltage source
across the diode for forward bias and place an ammeter in series with the diode and a
voltmeter across the diode. Slowly increase the voltage from zero and plot the forward
voltage versus the current.
6. A temperature increase would cause the barrier potential of a silicon diode to decrease
from
0.7 V to 0.6 V.
Section 2-3 Diode Models
7. (a) The diode is reverse-biased. (b) The diode is forward-biased.
(c) The diode is forward-biased. (d) The diode is forward-biased.
8. (a) VR 5 V 8 V -3 V
(b) VF 0.7 V
(c) VF 0.7 V
(d) VF 0.7 V
Chapter 2
9. (a) VR 5 V 8 V -3 V
(b) VF 0 V
(c) VF 0 V
(d) VF 0 V
10. Ignoring rR :
(a) VR 5 V 8 V -3 V
100 V 0.7 V
(b) IF 174 mA
560 10
VF I F rd VB (174 mA) (10 ) 0.7 V 2.44 V
30 V 30 V
(c) I tot 6.19 mA
Rtot 4.85 k
6.19 mA
IF 3.1 mA
2
VF I F rd 0.7 V (3.1 mA) (10 ) 0.7 V 0.731 V
(d) Approximately all of the current from the 20 V source is through the diode. No
current from the 10 V source is through the diode.
20 V 0.7 V
IF 1.92 mA
10 k 10
VF (1.92 mA) (10 ) 0.7 V 0.719 V
Section 2-4 Half-Wave Rectifiers
11. See Figure 2-1.
Figure 2-1
12. (a) PIV = Vp = 5 V (b) PIV = Vp = 50 V
Vp 200 V
13. VAVG 63.7 V
Chapter 2
V( p )in 0.7 V 5 V 0.7 V 4.3 V
14. (a) IF 91.5 mA
R 47 47
V( p ) in 0.7 V 50 V 0.7 V 49.3 V
(b) IF 14.9 mA
R 3.3 k 3.3 k
15. Vsec nV pri (0.2)120 V 24 V rms
16. Vsec nV pri (0.5)120 V 60 V rms
V p(sec) 1.414(60 V) 84.8 V
V p ( sec ) 84.8 V
Vavg ( sec ) 27.0 V
V 0.7 V
2
p ( sec ) (84.1 V) 2
PL ( p ) 32.1 W
RL 220
V
2
avg ( sec ) (27.0 V) 2
PL ( avg ) 3.31 W
RL 220
Section 2-5 Full-Wave Rectifiers
Vp 5V
17. (a) VAVG 1.59 V
2V p 2(100 V)
(b) VAVG 63.7 V
2V p 2(10 V)
(c) VAVG 10 V 10 V 16.4 V
2V p 2(40 V)
(d) VAVG 15 V 15 V 10.5 V
18. (a) Center-tapped full-wave rectifier
(b) V p ( sec ) (0.25)(1.414)120 V 42.4 V
V p ( sec ) 42.4 V
(c) 21.2 V
2 2
(d) See Figure 2-2. VRL 21.2 V 0.7 V 20.5 V
Figure 2-2
Chapter 2
V p ( sec )
0.7 V
2 20.5 V
(e) IF 20.5 mA
RL 1.0 k
(f) PIV 21.2 V 20.5 V 41.7 V
120 V
19. VAVG 60 V for each half
2
Vp
VAVG
V p VAVG (60 V) 186 V
20. See Figure 2-3.
Figure 2-3
VAVG( out ) (50 V)
21. PIV V p 78.5 V
2 2
22. PIV V p ( out ) 1.414(20 V) 28.3 V
23. See Figure 2-4.
Figure 2-4
Chapter 2
Section 2-6 Power Supply Filters and Regulators
24. Vr ( pp ) 0.5 V
Vr ( pp ) 0.5 V
r 0.00667
VDC 75 V
V p (in ) 30 V
25. Vr ( pp ) 8.33 V pp
fRL C (120 Hz)(600 )(50 F)
1 1
VDC 1 V p (in ) 1 30 V 25.8 V
2 fRL C (240 Hz)(600 )(50 F)
Vr ( pp ) 8.33 V
26. %r 100 100 32.3%
VDC 25.8 V
27. Vr ( pp ) (0.01) (18 V) 180 mV
1
Vr ( pp ) V p ( in )
fRL C
1 1
C V p ( in ) 18 V 556 F
fRLVr (120 Hz)(1.5 k)(180 mV)
V p ( in ) 80 V
28. Vr ( pp ) 6.67 V
fRL C (120 Hz)(10 k)(10 F)
1 1
VDC 1 V p ( in ) 1 80 V 76.7 V
2 fRL C (240 Hz)(10 k)(10 F)
Vr ( pp ) 6.67 V
r 0.087
VDC 76.7 V
29. V p ( sec ) (1.414)(36 V) 50.9 V
Vr ( rect ) V p ( sec ) 1.4 V 50.9 V 1.4 V 49.5 V
1 1
Neglecting Rsurge, Vr ( pp ) V p ( rect ) 49.5 V 1.25 V
fRL C (120 Hz)(3.3 k)(100 F)
1 Vr ( pp )
VDC 1 V p ( rect ) V p ( rect ) 49.5 V 0.625 V 48.9 V
2 fRL C 2
Chapter 2
30. V p ( sec ) 1.414(36 V) 50.9 V
See Figure 2-5.
Figure 2-5
V VFL 15.5 V 14.9 V
31. Load regulation NL 100% 100% 4%
VFL 14.9 V
32. VFL VNL (0.005)VNL 12 V (0.005)12 V 11.94 V
Section 2-7 Diode Limiters and Clampers
33. See Figure 2-6.
Figure 2-6
34. Apply Kirchhoff’s law at the peak of the positive half cycle:
(b) 25 V VR1 VR 2 0.7 V
2VR 24.3 V
24.3 V
VR 12.15 V
2
Vout VR 0.7 V 12.15 V 0.7 V 12.85 V
See Figure 2-7(a).
Chapter 2
11.3 V
(c) VR 5.65 V
2
Vout VR 0.7 V 5.65 V 0.7 V 6.35 V
See Figure 2-7(b).
4.3 V
(d) VR 2.15 V
2
Vout VR 0.7 V 2.15 V 0.7 V 2.85 V
See Figure 2-7(c).
Figure 2-7
35. See Figure 2-8.
Figure 2-8
Chapter 2
36. See Figure 2-9.
Figure 2-9
37. See Figure 2-10.
Figure 2-10
30 V 0.7 V
38. (a) Ip 13.3 mA
2.2 k
(b) Same as (a).
30 V (12 V 0.7 V)
39. (a) Ip 7.86 mA
2.2 k
30 V (12 V 0.7 V)
(b) Ip 8.5 mA
2.2 k
30 V (11.3 V)
(c) Ip 18.8 mA
2.2 k
30 V ( 12.7 V)
(d) Ip 19.4 mA
2.2 k
Chapter 2
40. See Figure 2-11.
Figure 2-11
41. (a) A sine wave with a positive peak at 0.7 V, a negative peak at 7.3 V, and a dc
value of
3.3 V.
(b) A sine wave with a positive peak at 29.3 V, a negative peak at 0.7 V, and a dc
value of
14.3 V.
(c) A square wave varying from 0.7 V to 15.3 V with a dc value of 7.3 V.
(d) A square wave varying from 1.3 V to 0.7 V with a dc value of 0.3 V.
42. (a) A sine wave varying from 0.7 V to 7.3 V with a dc value of 3.3 V.
(b) A sine wave varying from 29.3 V to 7.3 V with a dc value of 14.3 V.
(c) A square wave varying from 0.7 V to 15.3 V with a dc value of 7.3 V.
(d) A square wave varying from 1.3 V to 0.7 V with a dc value of 0.3 V.
Section 2-8 Voltage Multipliers
43. VOUT 2V p ( in ) 2(1.414)(20 V) 56.6 V
See Figure 2-12.
Figure 2-12
Chapter 2
44. VOUT( trip ) 3V p ( in ) 3(1.414)(20 V) 84.8 V
VOUT( quad ) 4V p ( in ) 4(1.414)(20 V) 113 V
See Figure 2-13.
Figure 2-13
Section 2-9 The Diode Datasheet
45. The PIV is specified as the peak repetitive reverse voltage 100 V.
46. The PIV is specified as the peak repetitive reverse voltage 1000 V.
47. I F(AVG ) 1.0 A
50 V
RL (min ) 50
1.0 A
Section 2-10 Troubleshooting
48. (a) Since VD 25 V 0.5VS , the diode is open.
(b) The diode is forward-biased but since VD 15 V VS , the diode is open.
(c) The diode is reverse-biased but since VR 2.5 V 0.5VS , the diode is shorted.
(d) The diode is reverse-biased and VR 0 V. The diode is operating properly.
49. VA VS1 25 V
VB VS1 0.7 V 25 V 0.7 V 24.3 V
VC VS2 0.7 V 8 V 0.7 V 8.7 V
VD VS2 8.0 V
Chapter 2
50. If a bridge rectifier diode opens, the output becomes a half-wave voltage, resulting in an
increased ripple at 60 Hz.
2V p 2(115 V)(1.414)
51. Vavg 104 V
The output of the bridge is correct. However, the 0 V output from the filter indicates that
the surge resistor is open or that the capacitor is shorted.
52. (a) Correct
(b) Incorrect. Open diode.
(c) Correct
(d) Incorrect. Open diode.
120 V
53. Vsec 24 V rms
5
V p ( sec ) 1.414(24 V) 33.9 V
The peak voltage for each half of the secondary is
V p ( sec ) 33.9 V
17 V
2 2
The peak inverse voltage for each diode is PIV 2(17 V) 0.7 V 34.7 V
The peak current through each diode is
V p ( sec )
0.7 V
2 17.0 V 0.7 V
Ip 49.4 mA
RL 330
The diode ratings exceed the actual PIV and peak current.
The circuit should not fail.
Device Application Problems
54. (a) Not plugged into ac outlet or no ac available at outlet. Check plug and/or breaker.
(b) Open transformer winding or open fuse. Check transformer and/or fuse.
(c) Incorrect transformer installed. Replace.
(d) Leaky filter capacitor. Replace.
(e) Rectifier faulty. Replace.
(f) Rectifier faulty. Replace.
55. The rectifier must be connected backwards.
56. 16 V with 60 Hz ripple
Chapter 2
Advanced Problems
1
57. Vr V p ( in )
fRL C
1 1
C V p ( in ) 35 V 177 F
fRLVr (120 Hz)(3.3 k)(0.5 V)
1
58. VDC 1 V p ( in )
2 fRL C
VDC 1
1
V p ( in ) 2 fRL C
1 V
1 DC
2 fRL C V p ( in )
1
C
V
2 fRL 1 DC
V
p ( in )
1 1
C 62.2 F
(240 Hz)(1.0 k)(1 0.933) (240 Hz)(1.0 k)(0.067)
Then
1 1
Vr V p ( in ) 15 V 2 V
fRL C (120 Hz)(1.0 k)(62.2 F)
59. The capacitor input voltage is
V p ( in ) (1.414)(24 V) 1.4 V 32.5 V
V p ( in ) 32.5 V
Rsurge 651 m
I surge 50 A
The nearest standard value is 680 m .
60. See Figure 2-14.
The voltage at point A with respect to ground is
VA 1.414(9 V) 12.7 V
Therefore,
VB 12.7 V 0.7 V 12 V
Vr 0.05 VB 0.05(12 V) 0.6 V peak to peak
1 1
C VB 12 V 245 F
fRLVr (120 Hz)(680 )(0.6 V)
Chapter 2
The nearest standard value is 270 F.
Let Rsurge 1.0 .
12 V
I surge ( max ) 12 A
1.0
12 V
I F(AV) 17.6 mA
680
PIV 2 V p ( out ) 0.7 V 24.7 V
Figure 2-14
61. See Figure 2-15.
I L ( max ) 100 mA
9V
RL 90
100 mA
Vr 1.414(0.25 V) 0.354 V
Vr 2(0.35 V) 0.71 V peak to peak
1
Vr 9 V
(120 Hz)(90 )C
9V
C 1174 F
(120 Hz)(90 )(0.71 V)
Chapter 2
Use C 1200 F.
Each half of the supply uses identical components. 1N4001 diodes are feasible since the
average current is (0.318)(100 mA) 31.8 mA.
Rsurge 1.0 will limit the surge current to an acceptable value.
Figure 2-15
62. See Figure 2-16.
Figure 2-16
63. VC1 (1.414)(120 V) 0.7 V 170 V
VC 2 2(1.414)(120 V) 2(0.7 V) 338 V
Chapter 2
Multisim Troubleshooting Problems
64. Diode shorted
65. Diode open
66. Diode open
67. Diode shorted
68. No fault
69. Diode shorted
70. Diode leaky
71. Diode open
72. Diode shorted
73. Diode shorted
74. Diode leaky
75. Diode open
76. Bottom diode open
77. Reduced transformer turns ratio
78. Open filter capacitor
79. Diode leaky
80. D1 open
81. Load resistor open
Chapter 3
Special-Purpose Diodes
Section 3-1 The Zener Diode
1. See Figure 3-1.
Figure 3-1
2. I ZK 3 mA
VZ 9 V
VZ 5.65 V 5.6 V 0.05 V
3. ZZ 5
I Z 30 mA 20 mA 10 mA
4. I Z 50 mA 25 mA 25 mA
VZ I Z Z Z (25 mA)(15 ) 0.375 V
VZ VZ VZ 4.7 V 0.375 V 5.08 V
5. T 70C 25C 45C
(6.8 V)(0.0004/ C)
VZ 6.8 V 6.8 C 0.12 V 6.92 V
45C
6. 5 W 5.3 mW/ C(100 C 25 C) 4.60 W.
7. From the data sheet
(a) Nominal zener voltage 36 V
(b) Maximum zener voltage 37.8 V
(c) Knee current IZK 0.25 mA
(d) Derating factor 6.67 mW/ C
(e) Temperature above which derating applies 50 C
Chapter 3
Section 3-2 Zener Diode Applications
8. VIN(min) VZ I ZK R 14 V (1.5 mA)(560 ) 14.8 V
9. VZ ( I Z I ZK ) Z Z (28.5 mA)(20 ) 0.57 V
VOUT VZ VZ 14 V 0.57 V 13.43 V
VIN(min) I ZK R VOUT (1.5 mA)(560 ) 13.43 V 14.3 V
10. VZ I Z Z Z (40 mA 30 mA)(30 ) 0.3 V
VZ 12 V VZ 12 V 0.3 V 12.3 V
VIN VZ 18 V 12.3 V
R 143
40 mA 40 mA
11. VZ 12 V 0.3 V 12.3 V
See Figure 3-2.
Figure 3-2
12. VZ(min) VZ I Z Z Z 5.1 V (49 mA 1 mA)(7 )
5.1 V (48 mA)(7 ) 5.1 V 0.336 V 4.76 V
VR 8 V 4.76 V 3.24 V
VR 3.24 V
IT 147 mA
R 22
I L(max) 147 mA 1 mA 146 mA
VZ(max) 5.1 V (70 mA 49 mA)(7 ) 5.1 V 147 mV 5.25 V
VR 8 V 5.25 V 2.75 V
2.75 V
IT 125 mA
22
I L(min) 125 mA 70 mA 55 mA
Chapter 3
VZ(max) VZ(min) 5.25 V 4.76 V
13. % Load regulation 100% 100% 10.3%
VZ(min) 4.76 V
14. With no load and VIN 6 V:
VIN VZ 6 V 5.1 V
IZ 31 mA
R ZZ 29
VOUT VZ I Z Z Z 5.1 V (49 mA 31 mA)(7 ) 5.1 V 0.126 V 4.97 V
With no load and VIN 12 V:
VIN VZ 12 V 5.1 V
IZ 238 mA
R ZZ 29
VOUT VZ I Z Z Z 5.1 V (238 mA 49 mA)(7 ) 5.1 V 1.32 V 6.42 V
VOUT 6.42 V 4.97 V
% Line regulation 100% 100% 24.2%
VIN 12 V 6 V
VNL VFL 8.23 V 7.98 V
15. % Load regulation 100% 100% 3.13%
VFL 7.98 V
VOUT 0.2 V
16. % Line regulation 100% 100% 4%
VIN 10 V 5 V
VNL VFL 3.6 V 3.4 V
17. % Load regulation 100% 100% 5.88%
VFL 3.4 V
Section 3-3 The Varactor Diode
18. At 5 V, C 20 pF
At 20 V, C 10 pF
C 20 pF 10 pF 10 pF (decrease)
19. From the graph, VR 3 V @ 25 pF
1
20. fr
2 LCT
1 1
CT 2 2
2 12.7 pF
4 Lf r 4 (2 mH)(1 MHz) 2
Since they are in series, each varactor must have a capacitance of 2CT 25.4 pF
21. Each varactor has a capacitance of 25.4 pF. Therefore, from the graph, VR must be
slightly less than 3 V.
Chapter 3
Section 3-4 Optical Diodes
24 V
22. IF 35.3 mA
680
From the graph, the radiant power is approximately 80 mW.
23. See Figure 3-3.
5 V 2.1 V
R 97
30 mA
The nearest standard 1% value is 97.6 or the nearest standard 5% value is 91 .
Figure 3-3
24. VF 2.2 V for I F 20 mA
9V
Maximum LEDs/branch 4
2.2 V
Select 3 LEDs/branch:
48
Number of branches 16
3
9 V 3(2.2 V)
RLIMIT 120
20 mA
Use sixteen 120 resistors.
25. VF 2.5 V for I F 30 mA
24 V
Maximum LEDs/branch 9.6
2.5 V
Select 5 LEDs/branch:
100
Number of branches 20
5
24 V 5(2.5 V)
RLIMIT 383
30 mA
See Figure 3-4.
Figure 3-4
Chapter 3
10 V
26. IR 50 A
200 k
VS 3V
27. (a) R 30 k
I 100 A
VS 3V
(b) R 8.57 k
I 350 A
VS 3V
(c) R 5.88 k
I 510 A
28. The microammeter reading will increase.
Section 3-5 The Solar Cell
29. The parts of a solar cell are p region, n region, conductive grid, conductive bottom layer,
and reflective coating.
Vout 15 V
30. Number of series connected cells 30
Vcell 0.5 V
Vout 15 V
31. I 1.5 mA
RL 10 k
10 mA
32. Connect seven t mA 6.67 of the 30-cell series connections in parallel.
1
I TOT 7(1.5 mA) 10.5 mA
Section 3-6 Other Types of Diodes
V 125 mV 200 mV 75 mV
33. R 750
I 0.25 mA 0.15 mA 0.10 mA
34. Tunnel diodes are used in oscillators.
35. The reflective ends cause the light to bounce back and forth, thus increasing the intensity
of the light. The partially reflective end allows a portion of the reflected light to be
emitted.
Section 3-7 Troubleshooting
36. (a) All voltages are correct.
(b) V3 should be 12 V. Zener is open.
Chapter 3
(c) V1 should be 120 V. Fuse is open.
(d) Capacitor C1 is open.
(e) R is open or D5 is shorted.
37. (a) With D5 open, VOUT 30 V.
(b) With R open, VOUT 0 V.
(c) With C leaky, VOUT has excessive 120 Hz ripple limited to 12 V.
(d) With C open, VOUT is full wave rectified voltage limited to 12 V.
(e) With D3 open, VOUT has 60 Hz ripple limited to 12 V.
(f) With D2 open, VOUT has 60 Hz ripple limited to 12 V.
(g) With T open, VOUT 0 V.
(h) With F open, VOUT 0 V.
Device Application Problems
38. (a) Faulty regulator
39. Incorrect transformer secondary voltage
40. LED open, limiting resistor open, faulty regulator, faulty bridge rectifier
12 V
41. IL 12 mA; Vreg 16 V 12 V 4 V
1 k
Preg (4 V)(12 mA) 48 mW
Datasheet Problems
42. From the datasheet of textbook Figure 3-7:
(a) @ 25C: PD(max) 1.0 W for a 1N4738A
(b) For a 1N4751A:
@ 70C; PD(max) 1.0 W (6.67 mW/ C)(20C) 1.0 W 133 mW 867 mW
@ 100C; PD(max) 1.0 W (6.67 mW/ C)(50C) 1.0 W 333 mW 667 mW
(c) I ZK 0.5 mA for a 1N4738A
(d) @ 25C: I ZM 1 W/27 V 37.0 mA for a 1N4750A
(e) Z Z 700 7.0 693 for a 1N4740A
Chapter 3
43. From the graph of textbook Figure 3-24:
(a) CMAX 60 pF
(b) CMIN 20 pF
CMAX 60 pF
(c) CR 3
CMIN 20 pF
44. From the datasheet of textbook 3-34:
(a) 9 V cannot be applied in reverse across a TSMF1000 because VR(max) 5 V.
(b) When 5.1 V is used to forward-bias the TSMF1000 for I F 20 mA, VF 1.3 V
5.1 V 1.3 V 3.8 V
R 190
20 mA 20 mA
(c) At 25C maximum power dissipation is 190 mW.
If VF 1.5 V and I F 50 mA, PD 75 mW. The power rating is not exceeded.
(d) For I F 40 mA, radiant intensity is approximately 0.9 mW/sr.
(e) For I F 100 mA, and 20, radiant intensity is 40% of maximum or
(0.4)(25 mW/sr) 10 mW /sr
45. From the datasheet of textbook Figure 3-47:
(a) With no incident light and a 10 k series resistor, the typical voltage across the
resistor is approximately VR (1 nA)(1 k) 1 V.
(b) Reverse current is greatest at about 940 nm.
(c) Sensitivity is maximum for 830 nm.
Advanced Problems
46. See Figure 3-5.
Figure 3-5
Chapter 3
47. VOUT(1) 6.8 V , VOUT(2) 24 V
48. For a 10 k load on each output:
VOUT1 6.8 V
I OUT(1) 0.68 mA
R1 10 k
V 24 V
I OUT(2) OUT2 2.4 mA
R2 10 k
VR1 120 V 6.8 V 113.2 V
113.2 V
I Z1 0.68 mA 112.5 mA
1 k
VR2 120 V 24 V 96 V
96 V
I Z2 2.4 mA 93.6 mA
1 k
I T 0.68 mA 2.4 mA 112.5 mA 93.6 mA 209.2 mA
The fuse rating should be 250 mA or 1/ 4 A.
49. See Figure 3-6.
Use a IN4738A zener.
I T 35 mA 31 mA 66 mA
24 V 8.2 V
R 239
66 mA
Figure 3-6
1 1
50. Cmax 2 103.4 pF
4 Lf min 4 (2 mH)(350 kHz)2
2 2
1 1
Cmin 2 2
17.5 pF
4 4 (2 mH)(850 kHz) 2
Lf max 2
To achieve this capacitance range, use an 826A varactor and change V2 to 30 V.
51. See Figure 3-7. From datasheet, VF 2.1 V for red LED.
VD 12 V 2.1 V
R 495
I 20 mA
Use standard value of 510 .
Figure 3-7
Chapter 3
52. See Figure 3-8.
Figure 3-8
Multisim Troubleshooting Problems
53. Zener diode open
54. Capacitor open
55. Zener diode shorted
56. Resistor open
Chapter 4
Bipolar Junction Transistors
Section 4-1 Bipolar Junction Transistor (BJT) Structure
1. npn has an n-type emitter and collector and a p-type base. The pnp has a p-type emitter
and emitter and an n-type base.
2. The term bipolar refers to the use of both holes and electrons as current carriers in the
transistor structure
3. Majority carriers in the base region of an npn transistor are holes.
4. Because of the narrow base region, the minority carriers invading the base region find a
limited number of partners for recombination and, therefore, move across the junction
into the collector region rather than out of the base lead.
Section 4-2 Basic BJT Operation
5. The base is narrow and lightly doped so that a small recombination (base) current is
generated compared to the collector current.
6. I B 0.02 I E 0.02(30 mA) 0.6 mA
I C I E I B 30 mA 0.6 mA 29.4 mA
7. The base must be negative with respect to the collector and positive with respect to the
emitter.
8. I C I E I B 5.34 mA 475 A 4.87 mA
Section 4-3 BJT Characteristics and Parameters
I C 8.23 mA
9. DC 0.947
I E 8.69 mA
I C 25 mA
10. DC 125
I B 200 A
11. I B I E I C 20.5 mA 20.3 mA 0.2 mA 200 A
I C 20.3 mA
DC 101.5
I B 200 A
Chapter 4
12. I E I C I B 5.35 mA 50 A 5.40 mA
I C 5.35 mA
DC 0.99
I E 5.40 mA
13. I C DC I E 0.96(9.35 mA) 8.98 mA
VR C 5V
14. IC 5 mA
RC 1.0 k
I C 5 mA
DC 100
I B 50 A
DC100
15. DC
0.99
DC 1 101
VBB VBE 3 V 0.7 V
16. IB 23 A
RB 101 k
I C DC I B 200(23 A) 4.6 mA
I E I C I B 4.6 mA 23 A 4.62 mA
VCE VCC I C RC 10 V (4.6 mA)(1.0 k) 5.4 V
17. I C does not change.
For VCC 10 V:
VCE VCC I C RC 10 V (4.6 mA)(1.0 k) 5.4 V
For VCC 15 V:
VCE 15 V (4.6 mA)(1.0 k) 10.7 V
VCE 10.7 V 5.4 V 5.3 V increase
VBB VBE 4 V 0.7 V 3.3 V
18. IB 702 A
RB 4.7 k 4.7 k
VCC VCE 24 V 8 V
IC 34 mA
RC 470
I E I C I B 34 mA 702 A 34.7 mA
I 34 mA
DC C 48.4
I B 702 A
Chapter 4
19. (a) VBE 0.7 V
VBB VBE 4.3 V
IB 1.1 mA
RB 3.9 k
I C DC I B 50(1.1 mA) 55 mA
VCE VCC I C RC 15 V (55 mA)(180 ) 5.10 V
VCB VCE VBE 5.10 V 0.7 V 4.40 V
(b) VBE 0.7 V
VBB VBE 3 V (0.7 V) 2.3 V
IB 85.2 A
RB 27 k 27 k
I C DC I B 125(85.2 A) 10.7 mA
VCE VCC I C RC 8 V (10.7 mA)(390 ) 3.83 V
VCB VCE VBE 3.83 V (0.7 V) 3.13 V
VCC 15 V
20. (a) I C(sat) 83.3 mA
RC 180
VBB VBE 5 V 0.7 V
IB 1.1 mA
RB 3.9 k
I C DC I B 50(1.1 mA) 55 mA
I C I C(sat)
Therefore, the transistor is not saturated.
VCC 8V
(b) I C(sat) 20.5 mA
RC 390
VBB VBE 3 V 0.7 V
IB 85.2 A
RB 27 k
I C DC I B 125(85.2 A) 10.7 mA
I C I C(sat)
Therefore, the transistor is not saturated.
21. VB 2 V
VE VB VBE 2 V 0.7 V 1.3 V
V 1.3 V
IE E 1.3 mA
RE 1.0 k
I C DC I E (0.98)(1.3 mA) 1.27 mA
0.98
DC DC 49
1 DC 1 0.98
I B I E I C 1.3 mA 1.27 mA 30 A
Chapter 4
22. (a) VB VBB 10 V
VC VCC 20 V
VE VB VBE 10 V 0.7 V 9.3 V
VCE VC VE 20 V 9.3 V 10.7 V
VBE 0.7 V
VCB VC VB 20 V 10 V 10 V
(b) VB VBB 4 V
VC VCC 12 V
VE VB VBE 4 V (0.7 V) 3.3 V
VCE VC VE 12 V (3.3) V 8.7 V
VBE 0.7 V
VCB VC VB 12 V (4 V) 8 V
23. For DC 100:
VB VBE 10 V 0.7 V
IE 930 A
RE 10 k
100
DC DC 0.990
1 DC 101
I C DC I E (0.990)(930 A) 921 A
For DC 150:
I E 930 A
DC 150
DC 0.993
1 DC 151
I C DC I E (0.993)(930 A) 924 A
I C 924 A 0.921 A 3 A
24. PD(max) VCE I C
PD(max) 1.2 W
VCE(max) 24 V
IC 50 mA
25. PD(max) 0.5 W (75C)(1 mW/ C) 0.5 W 75 mW 425 mW
Section 4-4 The BJT as an Amplifier
26. Vout AvVin 50(100 mV) 5 V
Vout 100 V
27. Av 33.3
Vin 300 mV
Chapter 4
RC 560
28. Av 56
re 10
Vc Vout AvVin 56(50 mV) 2.8 V
VBB VBE 2.5 V 0.7 V
29. IB 18 A
RB 100 k
I C DC I B 250(18 A) 4.5 mA
V VCE 9 V 4 V
RC CC 1.1 k
IC 4.5 mA
30. (a) DC current gain DC 50
(b) DC current gain DC 125
Section 4-5 The BJT as a Switch
VCC 5V
31. I C(sat) 500 A
RC 10 k
I C(sat) 500 A
I B(min) 3.33 A
DC 150
VIN(min) 0.7 V
I B(min)
RB
RB I B(min) VIN(min) 0.7 V
VIN(min) RB I B(min) 0.7 V (3.33 A)(1.0 M) 0.7 V 4.03 V
15 V
32. I C(sat) 12.5 mA
1.2 k
I C(sat)12.5 mA
I B(min) 250 A
DC 50
V 0.7 V 4.3 V
RB(min) IN 17.2 k
I B(min) 250 A
VIN(cutoff) 0 V
33. Assume VCE(sat) 0 V
VCC 5V
I C(sat0) 0.5 mA
RC 10 k
I C(sat) 0.5 mA
IB 5 mA
DC 100
VINPUT I B RB 0.7 V 0.75 V 0.7 V 1.45 V
Chapter 4
34. VINPUT 0.3 V is insufficient to forward bias the base-emitter junctions and turn either
transistor on, therefore the output voltage is equal to VCC .
Section 4-6 The Phototransistor
35. I C DC I (200)(100 A) 20 mA
36. I (50 lm/m 2 )(1 A/lm/m 2 ) 50 A
I E DC I (100)(50 A) 5 mA
37. I out (0.30)(100 mA) 30 mA
I OUT
38. 0.6
I IN
I OUT 10 mA
I IN 16.7 mA
0.6 0.6
Section 4-7 Transistor Categories and Packaging
39. See Figure 4-1.
Figure 4-1
40. (a) Small-signal
(b) Power
(c) Power
(d) Small-signal
(e) RF
Section 4-8 Troubleshooting
41. With the positive probe on the emitter and the negative probe on the base, the ohmmeter
indicates an open, since this reverse-biases the base-emitter junction. With the positive
probe on the base and the negative probe on the emitter, the ohmmeter indicates a very
low resistance, since this forward-biases the base-collector junction.
Chapter 4
42. (a) Transistor’s collector junction or terminal is open.
(b) Collector resistor is open.
(c) Operating properly.
(d) Transistor’s base junction or terminal open (no base or collector current).
5 V 0.7 V
43. (a) IB 63.2 A
68 k
9 V 3.2 V
IC 1.76 mA
3.3 k
I 1.76 mA
DC C 27.8
I B 63.2 A
4.5 V 0.7 V
(b) IB 141 A
27 k
24 V 16.8 V
IC 15.3 mA
470
I 15.3 mA
DC C 109
I B 141 A
Device Application Problems
44. Q1 OFF, Q2 ON
I R2 0, PR2 0 mW
I R1 0, PR2 0 mW
12 V 0.7 V
I R3 I R4 304 A
1.2 k 36 k
PR3 (304 A) 2 (1.2 k) 110 W
PR4 (304 A) 2 (36 k) 3.3 mW
12 V 0.176 V
I R5 19 mA
620
PR5 (19 mA) 2 (620 ) 224 mW
Q1 ON, Q2 OFF
12 V 0.7 V
I R2 151 A
75 k
PR2 (151 A) 2 (75 k) 1.7 mW
(0.7 V) 2
PR1 0.49 W
1.0 M
12 V 0.1 V
I R4 9.9 mA
1.2 k
PR4 (9.9 mA) 2 (1.2 k) 118 mW
I R3 0, PR3 0 mW
I R5 0, PR5 0 mW
Chapter 4
45. I C(max) 200 mA
VCC 12 V
RL (min) 60
I C(max) 200 mA
46. See Figure 4-2.
Figure 4-2
Datasheet Problems
47. From the datasheet of textbook Figure 4-20:
(a) For a 2N3904, VCEO(max) 40 V
(b) For a 2N3904, I C(max) 200 mA
(c) For a 2N3904 @ 25C, PD(max) 625 mW
(d) For a 2N3904 @ TC 50C, PD(max) 625 mW 5 mW/C(25C)
625 mW 125 mW 500 mW
(e) For a 2N3904 with I C 1 mA, hFE(min) 70
48. For an MMBT3904 with TA 65C:
PD(max) 350 mW (65C 25C)(2.8 mW/ C)
350 mW 40C(2.8 mW/ C) 350 mW 112 mW 238 mW
49. For a PZT3904 with TC 45C:
PD(max) 1 W (45C 25C)(8 mW/ C)
1 W 20C(8 mW/ C) 1 W 160 mW 840 mW
Chapter 4
50. For the circuits of textbook Figure 4-67:
3 V 0.7 V 2.3 V
(a) IB 6.97 mA
330 330
Let hFE 30
I C 30(6.97 mA) 209 mA
VCC VCE(sat) 30 V 0.2 V
I C(sat) 110 mA
RC 270
The transistor is saturated since I C cannot exceed 110 mA.
PD (0.2 V)(110 mA) 22 mW
At 50C, PD(max) 350 mW (50C 25C)(2.8 mW/ C) 280 mW
No parameter is exceeded.
(b) VCEO 45 V which exceeds VCEO(max) .
51. For the circuits of textbook Figure 4-68:
5 V 0.7 V 4.3 V
(a) IB 4.30 A
10 k 10 k
hFE(max) 300
I C 300(4.30 A) 129 mA
9V
I C(sat) 9 mA
1.0 k
The transistor is saturated.
3 V 0.7 V 2.3 V
(b) IB 23 A
100 k 100 k
hFE(max) 300
I C 300(23 A) 6.90 mA
12 V
I C(sat) 21.4 mA
560
The transistor is not saturated.
IC 10 mA
52. I B(min) 66.7 A
hFE(max) 150
IC 10 mA
I B(max) 200 A
hFE(min) 50
Chapter 4
53. For the circuits of textbook Figure 4-70:
8 V 0.7 V 7.3 V
(a) IB 107 A
68 k 68 k
hFE 150
I C 150(107 A) 16.1 mA
VC 15 V (16.1 mA)(680 ) 15 V 10.95 V 4.05 V
VCE 4.05 V 0.7 V 3.35 V
PD (3.35 V)(16.1 mA) 53.9 mW
At 40C, PD(max) 360 mW (40C 25C)(2.06 mW/ C) 329 mW
No parameters are exceeded.
5 V 0.7 V 4.3 V
(b) IB 915 A
4.7 k 4.7 k
hFE 300
I C 300(915 A) 274 mA
35 V 0.3 V
I C(sat) 73.8 mA
470
The transistor is in hard saturation. Assuming VCE(sat) 0.3 V,
PD (0.3 V)(73.8 mA) 22.1 mW
No parameters are exceeded.
Advanced Problems
DC
54. DC
1 DC
DC DC DC DC
DC DC (1 DC )
DC
DC
(1 DC )
55. I C 150(500 A) 75 mA
VCE 15 V (180 )(75 mA) 1.5 V
Since VCE(sat) 0.3 V @ I C 50 mA, the transistor comes out of saturation.
Chapter 4
56. From the datasheet, DC(min) 15 (for I C 100 mA)
150 mA
I B(max) 10 mA
15
3 V 0.7 V 2.3 V
RB(min) 230
10 mA 10 mA
Use the standard value of 240 for RB .
To avoid saturation, the load resistance cannot exceed about
9 V 1 V
53.3
150 mA
See Figure 4-3.
Figure 4-3
57. Since I B 10 mA for I C 150 mA,
9 V 0.7 V 8.3 V
RB(min) 830
10 mA 10 mA
Use 910 . The load cannot exceed 53.3 .
See Figure 4-4.
Figure 4-4
Chapter 4
58. RC(min) Av re 50(8 ) 400 (Use 430 )
12 V 5 V
IC 16.3 mA
430
Assuming hFE 100,
16.3 mA
IB 163 A
100
4 V 0.7 V
RB(max) 20.3 k (Use 18 k)
163 A
See Figure 4-5.
Figure 4-5
Multisim Troubleshooting Problems
59. RB shorted
60. RC open
61. Collector-emitter shorted
62. Collector-emitter open
63. RE leaky
64. Collector-emitter shorted
65. RB open
66. RC open
Chapter 5
Transistor Bias Circuits
Section 5-1 The DC Operating Point
1. A transistor must be biased correctly to prevent it from saturating or going into cutoff
when an input signal is appliedl.
2. The collector characteristic curve show how the collector current IC varies with VCE for
various values of IB.
3. The transistor is biased too close to saturation.
4. I C DC I B 75(150 A) 11.3 mA
VCE VCC I C RC 18 V (11.3 mA)(1.0 k) 18 V 11.3 V 6.75 V
Q-point: VCEQ 6.75 V , I CQ 11.3 mA
VCC 18 V
5. I C(sat) 18 mA
RC 1.0 k
6. VCE(cutoff) 18 V
7. Horizontal intercept (cutoff):
VCE VCC 20 V
Vertical intercept (saturation):
VCC 20 V
I C(sat) 2 mA
RC 10 k
VBB 0.7 V
8. IB
RB
VBB I B RB 0.7 V (20 A)(1.0 M) 0.7 V 20.7 V
I C DC I B 50(20 A) 1 mA
VCE VCC I C RC 20 V (1 mA)(10 k) 10 V
9. See Figure 5-1.
VCE VCC I C RC
Chapter 5
VCC VCE 10 V 4 V
RC 1.2 k
IC 5 mA
IC 5mA
IB 0.05 mA
DC 100
10 V 0.7 V
RB 186 k
0.05 mA
PD(min) VCE I C (4 V)(5 mA) 20 mW
Figure 5-1
VBB VBE 1.5V 0.7 V
10. IB 80 A
RB 10 k
VCC 8V
I C(sat) 20.5 mA
RC 390
I C DC I B 75(80 A) 6 mA
The transistor is biased in the linear region because
0 I C I C(sat) .
11. (a) I C(sat) 50 mA
(b) VCE(cutoff) 10 V
(c) I B 250 A
I C 25 mA
VCE 5 V
Chapter 5
12. (a) I C 42 mA
(b) Interpolating between I B 400 A and I B 500 A
I B 450 A
(c) VCE 1.5 V
See Figure 5-2.
Figure 5-2
Section 5-2 Voltage-Divider Bias
R2 4.7 k
13. VTH VCC 15 V 2.64 V
R1 R2 26.7 k
R1R2 (22 k)(4.7 k)
RTH 3.87 k
R1 R2 26.7 k
VTH VBE 2.64 V 0.7 V
IE 2.75 mA
RE RTH DC 680 3.87 k 150
VB I E RE VBE (2.75 mA)(680 ) 0.7 V 2.57 V
I E RIN(BASE) ( I E )(10 R2 ) (2.75 mA)(47 k)
DC(min) 50.3
VB VB 2.57 V
VCC 15 V
14. I C(sat) 6.88 mA
RC RE 2.18 k
VE(sat) I C(sat) RE (6.88 mA)(680 ) 4.68 V
VB VE(sat) 0.7 V 4.68 V 0.7 V 5.38 V
Chapter 5
R2 RIN(BASE)
VCC VB
R1 R2 RIN(BASE)
DCVB (150)(5.38 V)
RIN(BASE) 117 k
IE 6.88mA
( R2 RIN(BASE) )VCC VB ( R1 R2 RIN(BASE) )
( R2 RIN(BASE) )VCC ( R2 RIN(BASE) )VB R1VB
( R2 RIN(BASE) )(VCC VB ) R1VB
R1VB
( R2 RIN(BASE) ) 12.3 k
VCC VB
1 1 1
R2 RIN(BASE) 12.3 k
1 1 1
72.3S
R2 12.3 k 117 k
1
R2 13.7 k
72.3S
R2 2 k
15. VB VCC 15 V 1.25 V
R1 R2 24 k
VE 1.25 V 0.7 V 0.55 V
VE 0.55 V
IE 809 A
RE 680
I C 809 A
VCE VCC I C RC VE 15V (809 A)(1.5 k 680 ) 13.2 V
R2 15 k
16. VTH VCC 9 V 2.18 V
R1 R2 62 k
R1R2 (47 k)(15 k)
RTH 11.4 k
R1 R2 62 k
VTH VBE 2.18 V 0.7 V
IE 1.34 mA
RE RTH DC 1 k 11.4 k 110
I C I E 1.34mA
VC VCC I C RC 9V (1.34 mA)(2.2 k) 6.05 V
Chapter 5
VE I E RE (1.34 mA)(1.0 k) 1.34 V
VB VE VBE 1.34 V 0.7 V 2.04 V
17. See Figure 5-3.
Figure 5-3
R2 5.6 k
18. (a) VTH VCC (12 V) 1.74 V
R1 R2 38.6 k
R1R2 (5.6 k)(33 k)
RTH 4.79 k
R1 R2 38.6 k
VTH VBE 1.74 V 0.7 V
IE 4.12 mA
RE RTH DC 560 4.79 k 150
VB I E RE VBE (4.12 mA)(560 k) 0.7 V 2.31 V 0.7 V 1.61 V
VTH VBE 1.74 V 0.7 V
(b) IE 3.72 mA
RE RTH DC 560 4.79 k 150
VB I E RE VBE (3.72 mA)(560 k) 0.7 V 2.08 V 0.7 V 1.38 V
19. (a) VEQ VB 0.7 V 1.61 V 0.7 V 0.91 V
VEQ 0.91 V
I CQ I E 1.63 mA
RE 560
VCQ VCC I C RC 12 V (1.63 mA)(1.8 k) 9.07 V
VCEQ VCQ VEQ 9.07 V (0.91 V) 8.16 V
(b) PD(min) I CQVCEQ (1.63 mA)(8.16 V) 13.3 mW
Chapter 5
20. VB 1.61 V
VCC VB 12 V (1.61 V)
I1 315 A
R1 33 k
VB 1.61 V
I2 2.88 A
R2 5.6 k
I B I1 I 2 315 A 288 A 27 A
Section 5-3 Other Bias Methods
21. Using Equation 5-9:
VEE VBE ( 5 V) 0.7 V 4.3 V
IE 1.86 mA
RE RB DC 2.2 k 10 k 100 2.2 k 0.1 k
I C I E 1.86 mA
IC 1.86 mA
IB 18.6 A
100
VB I B RB (18.6 A)(10 k) 0.186 V
VE VB 0.7 V 0.186 0.7 V 0.886 V
VC VCC I C RC 5 V (0.186 mA)(1.0 k) 3.14 V
22. Assume VCE 0 V at saturation.
VE 0.886 V
so, VC(sat) 0.886
VCC VC(sat) 5 V ( 0.886 V)
I C(sat) 5.89 mA
RC 1.0 k
VRE 4.11 V
RE(min) 698
I C(sat) 5.89 mA
23. At 100°C:
VBE 0.7 V (2.5 mV/ C)(75C) 0.513V
VEE VBE (5V) 0.513V 4.49 V
IE 1.95 mA
RE RB DC 2.2 k 10 k 100 2.3k
At 25°C:
I E 1.86 mA (from problem 19)
I E 1.95 mA 1.86 mA 0.09 mA
Chapter 5
24. A change in DC does not affect the circuit when RE RB / DC .
Since
VEE VBE
IE
RE RB DC
In the equation, if RB /DC is much smaller than RE , the effect of DC is negligible.
25. Assume DC 100.
VEE VE 10 V 0.7 V
IC IE 16.3 mA
RE RB / 470 10 k /100
VCE VEE VCC I C ( RC RE ) 20 V 13.1 V 6.95 V
26. VB 0.7 V
VCC VBE 3 V 0.7 V
IC 1.06 mA
RC RB / DC 1.8k 33 k /90
VC VCC I C RC 3 V (1.06 mA)(1.8 k) 1.09 V
27. I C 1.06 mA from Problem 26.
I C 1.06 mA (0.25)(1.06 mA) 0.795 mA
VCC VBE
IC
RC RB / DC
VCC VBE I C RB / DC 3 V 0.7 V (0.795 mA)(33 k)/90
RC 2.53 k
IC 0.795 mA
28. I C 0.795 mA from Problem 27.
VCE VCC I C RC 3 V (0.795 mA)(2.53 k) 0.989 V
PD(min) VCE I C (0.989 V)(0.795 mA) 786 W
Chapter 5
29. See Figure 5-4.
VCC VBE 12 V 0.7 V
IC 7.87 mA
RC RB / DC 1.2 k 47 k /200
VC VCC I C RC 12 V (7.87 mA)(1.2 k) 2.56 V
Figure 5-4
30. VBB VCC ; VE 0 V
VCC 0.7 V 12 V 0.7 V 11.3 V
IB 514 A
RB 22 k 22 k
I C DC I B 90(514 A) 46.3 mA
VCE VCC I C RC 12 V (46.3 mA)(100 ) 7.37 V
31. I CQ 180(514 A) 92.5 mA
VCEQ 12 V (92.5 mA)(100 ) 2.75 V
32. IC changes in the circuit with a common VCC and VBB supply because a change in VCC
causes IB to change which, in turn, changes IC.
VBB VBE 9 V 0.7 V
33. IB 553 A
RB 15 k
VCC 9V
I C(sat) 90 mA
RC 100
For DC 50:
I C DC I B 50(553 A) 27.7 mA
VCE VCC I C RC 9 V (27.7 mA)(100 ) 6.23 V
Chapter 5
For DC 125:
I C DC I B 125(553 A) 69.2 mA
VCE VCC I C RC 9 V (69.2 mA)(100 ) 2.08 V
Since I C I C(sat) for the range of DC , the circuit remains biased in the linear region.
VCC 9V
34. I C(sat) 90 mA
RC 100
At 0°C:
DC 110 110(0.5) 55
VCC VBE 9 V 0.7 V
IB 553 A
RB 15 k
I C DC I B 55(553 A) 30.4 mA
VCE VCC I C RC 9 V (30.4 mA)(100 ) 5.96 V
At 70°C:
DC 110 110(0.75) 193
I B 553 A
I C DC I B 193(553 A) 107 mA
I C I C(sat) , therefore the transistor is in saturation at 70°C.
I C I C(sat) I C(0°) 90 mA 30.4 mA 59.6 mA
VCE VCE(0) VCE(sat) 5.96 V 0 V 5.96 V
Section 5-4 Troubleshooting
35. The transistor is off; therefore, V1 0 V, V2 0 V, V3 8 V.
36. V1 0.7 V, V2 0 V
8 V 0.7 V 0.7 V
IB 221 A 70 A 151 A
33 k 10 k
I C 200(151 A) 30.2 mA
8V
I C(sat) 3.64 mA, so VC VE 0 V
2.2 k
Chapter 5
If the problem is corrected,
10 k
V1 8 V 1.86 V
10 k 33 k
V2 VE 1.86 V 0.7 V 1.16 V
1.16 V
IE 1.16 mA
1.0 k
V3 VC 8 V (1.16 mA)(2.2 k) 5.45 V
37. (a) Open collector
(b) No problems
(c) Transistor shorted from collector-to-emitter
(d) Open emitter
38. For DC 35:
4.5 k
VB (10 V) 3.1 V
14.5 k
For DC 100:
5.17 k
VB (10 V) 3.4 V
15.17 k
The measured base voltage at point 4 is within the correct range.
VE 3.1 V 0.7 V 2.4 V
2.4 V
IC IE 3.53 mA
680
VC 10 V (3.53 mA)(1.0 k) 6.47 V
Allowing for some variation in VBE and for resistor tolerances, the measured collector and
emitter voltages are correct.
39. (a) The 680 Ω resistor is open:
Meter 1: 10 V
Meter 2: floating
5.6 k
Meter 3: VB (10 V) 3.59 V
15.6 k
Meter 4: 10 V
(b) The 5.6 kΩ resistor is open.
9.3 V
IB 275 A
10 k 35(680 )
Chapter 5
I C 35(275 A) 9.6 mA
10 V
I C(sat) 5.95 mA
1680
The transistor is saturated.
Meter 1: 10 V
Meter 2: (5.95 mA)(680 Ω) = 4.05 V
Meter 3: 4.05 V + 0.7 V = 4.75 V
Meter 4: 10 V – (5.95 mA)(1.0 kΩ) = 4.05 V
(c) The 10 kΩ resistor is open. The transistor is off.
Meter 1: 10 V
Meter 2: 0 V
Meter 3: 0 V
Meter 4: 10 V
(d) The 1.0 kΩ resistor is open. Collector current is zero.
Meter 1: 10 V
Meter 2: 1.27 V – 0.7 V = 0.57 V
5.6 k 680
Meter 3: (10 V) 0.7 V 0.57 V 0.7 V 1.27 V
10 k 5.6 k 680
Meter 4: floating
(e) A short from emitter to ground.
Meter 1: 10 V
Meter 2: 0 V
Meter 3: 0.7 V
(10 V 0.7 V) 9.3 V
IB 0.93 mA
10 k 10 k
I C(min) 35(0.93 mA) 32.6 mA
10 V
I C(sat) 10 mA
1.0 k
The transistor is saturated.
Meter 4: 0 V
(f) An open base-emitter junction. The transistor is off.
Meter 1: 10 V
Meter 2: 0 V
5.6 k
Meter 3: (10 V) 3.59 V
15.6 k
Meter 4: 10 V
Chapter 5
Devices Application Problems
40. With R1 open:
VB 0 V, VE 0 V, VC VCC 9.1 V
41. Faults that will cause the transistor of textbook Figure 5-29(a) to go into cutoff:
R1 open, R2 shorted, base lead or BE junction open.
42. At 45°C: RTherm 2.7 k
RTherm 2.7 k
VB 9 V 9 V 3.28 V
R1 RTherm 7.4 k
VE VB 0.7 V 2.58 V
VE 2.58 V
IE IC 5.49 mA
R3 470
VC VOUT 9 V (5.49 mA)(1 k) 3.51 V
At 48°C: RTherm 1.78 k
1.78 k
VB 9 V 2.47 V
6.48 k
VE 2.47 V 0.7 V 1.77 V
1.77 V
IE IC 3.77 mA
470
VC VOUT 9 V (3.77 mA)(1 k) 5.23 V
At 53°C: RTherm 1.28 kΩ
1.28 k
VB 9 V 1.93 V
5.98 k
VE 1.93 V 0.7 V 1.23 V
1.23 V
IE IC 2.62 mA
470
VC VOUT 9 V (2.62 mA)(1 k) 6.38 V
43. The following measurements would indicate an open CB junction:
VC = VCC = +9.1 V
VB normal
VE 0 V
Chapter 5
Datasheet Problems
44. For T = 45°C and R2 = 2.7 kΩ
RIN(base) 2.7 k (30)(470 ) 2.7 k 14.1 k 2.27 k min
RIN(base) 2.7 k (300)(470 ) 2.7 k 141 k 2.65 k max
2.27 k 2.27 k
VB(min) 9.1 V 9.1 V 2.62 V
2.27 k 5.6 k 7.87
VE(min) 2.62 V 0.7 V 1.92 V
1.92 V
So, I C I E 4.09 mA
470
VC(max) 9.1 V (4.09 mA)(1.0 k) 5.01 V
2.65 k 2.65 k
VB(max) 9.1 V 9.1 V 2.62 V
2.65 k 5.6 k 8.25 k
VE(max) 2.92 V 0.7 V 2.22 V
2.22 V
So, I C I E 4.73 mA
470
VC(min) 9.1 V (4.73 mA)(1.0 k) 4.37 V
For T = 55°C and R2 = 1.24 kΩ:
RIN(base) 1.24 k (30)(470 ) 1.24 k 14.1 k 1.14 k min
RIN(base) 1.24 k (300)(470 ) 1.24 k 141 k 1.23 k max
1.14 k 1.14 k
VB(min) 9.1 V 9.1 V 1.54 V
1.14 k 5.6 k 6.74 k
VE(min) 1.54 V 0.7 V 0.839 V
0.839 V
So, I C I E 1.78 mA
470
VC(max) 9.1 V (1.78 mA)(1.0 k) 7.32 V
1.23 k 1.23 k
VB(max) 9.1 V 9.1 V 1.64 V
1.23 k 5.6 k 6.83 k
VE(max) 1.64 V 0.7 V 0.938 V
0.938 V
So, I C I E 2.0 mA
470
VC(min) 9.1 V (2.0 mA)(1.0 k) 7.10 V
Chapter 5
45. At T = 45°C for minimum DC :
PD(max) (5.01 V 1.92 V)(4.09 mA) (3.09 V)(4.09 mA) 12.6 mW
At T = 55°C for minimum DC :
PD(max) (7.32 V 0.839 V)(1.78 mA) (6.48 V)(1.78 mA) 11.5 mW
For maximum beta values, the results are comparable and nowhere near the maximum.
PD(max) 625 mW (5.0 m/ C)(30C) 475 mW
No ratings are exceeded.
46. For the datasheet of Figure 5-49 in the textbook:
(a) For a 2N2222A, I C(max) 1 A continuous
(b) For a 2N2118A, VEB(max) 6.0 V
47. For a 2N2222A @ T = 100°C:
PD(max) 0.8 W (4.57 mW/ C)(100C 25C) 0.8 W 343 mW 457 mW
48. If IC changes from 1 mA to 500 mA in a 2N2219A, the percentage change in DC is
30 50
DC 100% 40%
50
Advanced Problems
49. See Figure 5-5.
VCC VCEQ 15 V 5 V
RC 2 k
I CQ 5 mA
Assume DC 100.
I CQ 5 mA
I BQ 50 A
DC 100
VCC VBE 15 V 0.7 V
RB 286 k
I BQ 50 A
Figure 5-5
Chapter 5
50. See Figure 5-6.
Assume DC 200.
I CQ 10 mA
I BQ 50 A
DC 200
Let RB 1.0 k
12 V (50 A)(1.0 k) 0.7 V 11.3 V
RE 1.13 k
10 mA 10 mA
12 V ( 12 V 11.3 V 4 V) 8.7 V
RC 870
10 mA 10 mA
870 Ω and 1.13 kΩ are not standard values. RC 820 and RE 1.2 k give
I CQ 9.38 mA, VCEQ 5.05 V.
Figure 5-6
51. See Figure 5-7.
DC(min) 70. Let RE 1.0 k.
VE I E RE 1.5 mA(1.0 k) 1.5 V
VB 1.5 V 0.7 V 2.2 V
VCC VCEQ VE 9 V 1.5 V 3 V
RC 3 k
I CQ 1.5 mA
VCC 9V
R1 R2 2.57 k min
I CC(max) I CQ 5 mA 1.5 mA
Chapter 5
Assume DC RE R2 . The ratio of bias resistors equals the ratio of the voltages as
follows.
R1 6.8 V
3.09
R2 2.2 V
R1 3.09 R2
R1 R2 R2 3.09 R2 2.57 k
4.09 R2 2.57 k
2.57 k
R2 628
4.09
So, R2 620 and R1 1.92 k 2 k.
Figure 5-7
From this,
DCVB (70)(2.2 V)
RIN(base) 103 kW >> R2
IE 1.5 mA
620
so, VB 9 V 2.13 V
2.62 k
VE 2.13 V 0.7 V 1.43 V
1.43 V
I CQ I E 1.43 mA
1.0 k
VCEQ 9 V (1.43 mA)(1.0 k 3 k) 3.28 V
Chapter 5
52. See Figure 5-8.
DC 75.
10 mA
I BQ 133 A
75
VCC VCE 5 V 1.5 V
RC 350 (use 360 Ω)
I CQ 10 mA
VCE 0.7 V 1.55 V 0.7 V
RB 6 k (use 6.2 kΩ)
I BQ 133 A
5 V 0.7 V
I CQ 9.71 mA
360 6.2 k /75
VCEQ VC 5 V (9.71 mA)(360 ) 1.50 V
Figure 5-8
53. The 2N3904 in textbook Figure 5-47 can be replaced with a 2N2222A and maintain the
same voltage range from 45°C to 55°C because the voltage-divider circuit is essentially β
independent and the DC parameters of the two transistors are comparable.
54. For the 2N2222A using the datasheet graph in textbook Figure 5-50 at IC = 150 mA
and VCE = 1.0 V:
At T = –55°C, hFE(min) = (0.45)(50) = 22.5
At T = 25°C, hFE(min) = (0.63)(50) = 31.5
At T = 175°C, hFE(min) = (0.53)(50) = 26.6
55. If the valve interface circuit loading of the temperature conversion circuit changes from
100 kΩ to 10 kΩ, the Q-point will have a reduced VCEQ because the current through RC
will consist of the same IC and a larger IL. ICQ is unaffected in the sense that the transistor
collector current is the same, although the collector resistance current is larger. The
transistor saturates sooner so that lower temperatures do not register as well, if at all.
Chapter 5
56. It is not feasible to operate the circuit from a 5.1 V dc supply and maintain the same
range of output voltages because the output voltage at 60°C must be 6.478 V.
Multisim Troubleshooting Problems
57. RC open
58. RB open
59. R2 open
60. Collector-emitter shorted
61. RC shorted
62. Base-emitter open
Chapter 6
BJT Amplifiers
Section 6-1 Amplifier Operation
1. Slightly greater than 1 mA minimum
2. From the graph of Figure 6-4, the highest value of dc collector current is about 6 mA.
3. One end of the ac load line intersects the horizontal axis at Vce(curoff). The other end
intersects the vertical axis at Ic(sat).
Section 6-2 Transistor AC Models
4. The r parameters are re (ac emitter resistance), rc (ac collector resistance), rb (ac base
resistance), alphaac (ac alpha), betaac (ac beta). The h parameters are hi (input
impedance), hr (voltage feedback ratio), hf (forward current gain), ho (outut admittance)
25 mV 25 mV
5. re 8.33
IE 3 mA
6. ac h fe 200
7. I C DC I B 130(10 A) 1.3 mA
IC1.3 mA
IE 1.31 mA
DC 0.99
25 mV 25 mV
re 19
IE 1.31 mA
I C 2 mA
8. DC 133
I B 15 A
I C 0.35 mA
ac 117
I B 3 A
Chapter 6
Section 6-3 The Common-Emitter Amplifier
9. See Figure 6-1.
Figure 6-1
R2 4.7 k
10. (a) VB VCC 15 V 2.64 V
R1 R2 26.7 k
(b) VE = VB – 0.7 V = 2.64 – 0.7 V = 1.94 V
VE 1.94 V
(c) IE 1.94 mA
RE 1.0 k
(d) I C I E 1.94 mA
(e) VC = VCC – ICRC = 15 V – (1.94 mA)(2.2 kΩ) = 11.6 V
11. ICC = IBIAS + IC
V 2.64 V
I BIAS B 562 A
R2 4.7 k
ICC = 562 μA + 1.94 mA = 2.50 mA
P = ICCVCC = (2.5 mA)(15 V) = 37.5 mW
4.7 k
12. (a) VB 15V 2.64 V
4.7 k 22 k
VE = 2.64 V – 0.7 V = 1.94 V
1.94 V
IE 1.94 mA
1.0 k
25 mV 25 mV
re 12.9
IE 1.94 mA
Rin (base ) ac re RE 100(1012.9 ) 101 k
Chapter 6
(b) Rin Rin (base ) R1 R2 101 k 22 k 4.7 k 3.73 k
RC 2.2 k
(c) Av 2.17
RE re 12.02
13. (a) Rin (base) ac re 100(12.9 ) 1.29 k
(b) Rin 1.29 k 22 k 4.7 k 968
RC 2.2 k
(c) Av 171
re 12.9
14. (a) Rin (base) ac re 100(12.9 ) 1.29 k
(b) Rin 1.29 k 22 k 4.7 k 968
Rc RC RL 2.2 k 10 k
(c) Av 140
re re 12.9
R2 12 k
15. (a) VTH VCC 18 V 3.66 V
R1 R2 59 k
R1R2 (47 k)(12 k )
RTH 9.56 k
R1 R2 59 k
VTH VBE 3.66 V 0.7 V
IE 2.63 mA
RE RTH DC 1 k 9.56 k 75
(b) VE = IERE = (2.63 mA)(1 kΩ) = 2.63 V
(c) VB = VE + VBE = 2.63 V + 0.7 V = 3.76 V
(d) I C I E 2.63 mA
(e) VC = VCC – ICRC = 18 V – (2.63 mA)(3.3 kW) = 9.32 V
(f) VCE = VC – VE = 9.32 V – 2.63 V = 6.69 V
16. From Problem 15, IE = 2.63 mA
25 mV 25 mV
(a) Rin (base) ac re ac 70 665
IE 2.63 mA
(b) Rin R1 R2 Rin (base ) 47 k 12 k 665 622
RC RL 3.3 k 10 k
(c) Av 261
re 9.5
(d) Ai = βac = 70
(e) Ap = AvAi = (261)(70) = 18,270
Chapter 6
Rin 640
17. Vb Vin 12 V
Rin Rs 640 600
Attenuation of the input network is
Rin 640
0.516
Rin Rs 640 600
Av 0.516 Av 0.516(253) 131
θ = 180°
R2 3.3 k
18. VTH VCC 8 V 1.73 V
R1 R2 15.3 k
R1 R2 (12 k)(3.3 k )
RTH 2.59 k
R1 R2 15.3 k
VTH VBE 1.73 V 0.7 V
IE 8.78 mA
RE RTH DC 100 2.59 k 150
25 mV 25 mV
re 2.85
IE 8.78 mA
Maximum gain is at Re = 0 Ω
RC 330
Av (max) 116
re 2.85
Minimum gain is at Re = 100 Ω.
RC 330
Av (min) 3.21
RE re 2.85
R2 3.3 k
19. VTH VCC 8 V 1.73 V
R1 R2 15.3 k
R1R2 (12 k)(3.3 k )
RTH 2.59 k
R1 R2 15.3 k
VTH VBE 1.73 V 0.7 V
IE 8.78 mA
RE RTH DC 100 2.59 k 150
25 mV 25 mV
re 2.85
IE 8.78 mA
Maximum gain is at Re = 0 Ω
RC RL 330 600
Av (max) 74.7
re 2.85
Chapter 6
Minimum gain is at Re = 100 Ω.
RC RL 213
Av (min) 2.07
RE re 102.85
20. Rin R1 R2 ac re 3.3 k 12 k 150(3.25 ) 410
Attenuation of the input network is
Rin 410
0.578
Rin Rs 410 300
Rc 330 1.0 k
Av 76.3
re 3.25
Av 0.5777 Av 0.578(76.3) 44.1
21. See Figure 6-2.
25 mV
re 9.8
2.55 mA
Re 10re
Set Re = 100 Ω
The gain is reduced to
RC 3.3 k
Av 30.1
Re re 109.8
Figure 6-2
Chapter 6
Section 6-4 The Common-Collector Amplifier
R2 4.7 k
22. VB VCC 5.5 V 1.76 V
R1 R2 14.7 k
VB 0.7 V 1.76 V 0.7 V
IE 1.06 mA
RE 1.0 k
25 mV
re 23.6
1.06 mA
RE 1.0 k
Av 0.977
RE re 1.0 k 23.6
23. Rin R1 R2 ac re RE R1 R2 ac RE 10 k 4.7 k 100 k 3.1 k
R2 4.7 k
VOUT VB 0.7 V VCC 0.7 V 5.5 V 0.7 V 1.06 V
R1 R2 14.7 k
Re
24. The voltage gain is reduced because Av .
Re re
R2 4.7 k
25. VB VCC 5.5 V 1.76 V
R1 R2 14.7 k
VB VBE 1.76 V 0.7 V
IE 1.06 mA
RE 1.0 k
25 mV 25 mV
re 23.6
IE 1.06 mA
RE RL
Av
re RE RL
Av re RE RL RE RL
RE RL Av RE RL Av re
RE RL 1 Av Av re
Av re 09(23.6 )
RE RL 212.4
v
1 A 1 0.9
RL RE 212.4 RL 212.4 RE
RL RE 212.4 RL 212.4 RE
212.4 RE (212.4 )(1000 )
RL 270
RE 212.4 1000 212.4
Chapter 6
26. (a) VC1 = 10 V
R2 22 k
VB1 VCC 10 V 4 V
R1 R2 55 k
VE1 = VB1 – 0.7 V = 4 V – 0.7 V = 3.3 V
VC2 = 10 V
VB2 = VE1 = 3.3 V
VE2 = VB2 – 0.7 V = 3.3 V – 0.7 V = 2.6 V
(b) DC1 DC2 (150)(100) 15,000
DC
VE1 0.7 V 2.6 V
(c) I E1 17.3 A
DC2 RE 100(1.5 k)
25 mV 25 mV
re1 1.45 k
I E1 17.3 A
VE2 2.6 V
I E2 1.73 mA
RE 1.5 k
25 mV 25 mV
re2 14.5
I E2 17.3 mV
(d) Rin R1 R2 Rin (base1)
Rin (base1) ac1 ac 2 RE (150)(100)(1.5 k) 22.5 M
Rin 33 k 22 k 22.5 M 13.2 k
27. Rin (base ) ac1 ac 2 RE (150)(100)(1.5 k) 22.5 M
Rin R2 R1 Rin (base ) 22 k 33 k 22.5 M 13.2 k
Vin 1V
I in 75.8 A
Rin 13.2 k
Vin 1V
I in (base1) 44.4 nA
Rin (base1) 22.5 M
I e ac1 ac 2 I in (base1) (150)(100)(44.4 nA) 667 A
I e 667 A
Ai 8.8
I in 75.8 A
Chapter 6
Section 6-5 The Common-Base Amplifier
28. The main disadvantage of a common-base amplifier is low input impedance. Another
disadvantage is unity current gain.
R2 10 k
29. VE VCC VBE 24 V 0.7 V 6.8 V
R1 R2 32 k
6.8V
IE 10.97 mA
620
25 mV 25 mA
Rin ( emitter ) re 2.28
IE 10.97 mA
RC 1.2 k
Av 526
re 2.28
Ai 1
Ap Ai Av 526
30. (a) Common-base (b) Common-emitter (c) Common-collector
Section 6-6 Multistage Amplifiers
31. Av Av1 Av 2 (20)(20) 400
32. Av (dB) 10 dB + 10 dB + 10 dB = 30 dB
20 log Av 30 dB
30
log Av 1.5
20
Av 31.6
R2 8.2 k
33. (a) VE VCC VBE 15 V 0.7 V 2.29 V
R1 R2 33 k 8.2 k
VE 2.29 V
IE 2.29 mA
RE 1.0 k
25mV 25mA
re 10.9
IE 2.29 mA
Rin (2) R6 R5 ac re 8.2 k 33 k 175(10.9 ) 1.48 k
RC Rin (2) 3.3 k 1.48 k
Av1 93.6
re 10.9
RC 3.3k
Av 2 303
re 10.9
Chapter 6
(b) Av Av1 Av 2 (93.6)(303) 28,361
(c) Av1(dB) 20 log(93.6) 39.4 dB
Av 2(dB) 20 log(303) 49.6 dB
Av (dB) 20 log(28,361) 89.1 dB
RC Rin (2) 3.3 k 1.48 k
34. (a) Av1 93.6
re 10.9
RC RL 3.3 k 18 k
Av 2 256
re 10.9
(b) Rin (1) R1 R2 ac re 33 k 8.2 k 175(10.9 ) 1.48 k
Attenuation of the input network is
Rin (1) 1.48k
0.95
Rin (1) Rs 1.48k 75
Av (0.95) Av1 Av 2 (0.95)(93.6)(256) 22,764
(c) Av1(dB) 20 log(93.6) 39.4 dB
Av 2(dB) 20 log(256) 48.2 dB
Av (dB) 20 log(22,764) 87.1 dB
R2 22 k
35. VB1 VCC 12 V 2.16 V
R1 R2 122 k
VE1 = VB1 – 0.7 V = 1.46 V
VE1 1.46 V
I C1 I E1 0.311 mA
R4 4.7 k
VC1 = VCC – IC1R3 = 12 V – (0.311 mA)(22 kΩ) = 5.16 V
VB2 = VC1 = 5.16 V
VE2 = VB2 – 0.7 V = 5.16 V – 0.7 V = 4.46 V
VE2 4.46 V
I C2 I E2 0.446 mA
R6 10 k
VC2 = VCC – IC2R5 = 12 V – (0.446 mA)(10 kΩ) = 7.54 V
25mV 25mV
re2 56
I E2 0.446 mA
Rin (2) ac re2 (125)(56 ) 7 k
Chapter 6
25 mV 25 mV
re1 80.4
I E1 0.311 mA
R3 Rin (2) 22 k 7 k
Av1 66
re1 80.4
R5 10 k
Av 2 179
re2 56
Av Av1 Av 2 (66)(179) 11,814
36. (a) 20 log(12) = 21.6 dB
(b) 20 log(50) = 34.0 dB
(c) 20 log(100) = 40.0 dB
(d) 20 log(2500) = 68.0 dB
V V
37. (a) 20 log 2 3 dB (b) 20 log 2 6 dB
V1 V1
V 3 V 6
log 2 0.15 log 2 0.3
V1 20 V1 20
V2 V2
1.41 2
V1 V1
V V2
(c) 20 log 2 10 dB (d) 20 log 20 dB
V1 V1
V 10 V 20
log 2 0.5 log 2 1
V1 20 V1 20
V2 V2
3.16 10
V1 V1
V
(e) 20 log 2 40 dB
V1
V 40
log 2 2
V1 20
V2
100
V1
Chapter 6
Section 6-7 The Differential Amplifier
38. Determine IE for each transistor:
VR E 14.3 V
IRE 6.5 mA
RE 2.2 k
IRE
I E(Q1) I E(Q 2) 3.25 mA
2
Determine IC for each transistor:
IC(Q1) = α1IE(Q1) = 0.980(3.25 mA) = 3.185 mA
IC(Q2) = α2IE(Q2) = 0.975(3.25 mA) = 3.169 mA
Calculate the collector voltages:
VC(Q1) = 15 V – (3.185 mA)(3.3 kΩ) = 4.49 V
VC(Q2) = 15 V – (3.169 mA)(3.3 kΩ) = 4.54 V
The differential output voltage is:
VOUT = VC(Q2) – VC(Q1) = 4.54 V – 4.49 V = 0.05 V = 50 mV
39. V1 measures the differential output voltage.
V2 measures the noninverting input voltage.
V3 measures the single-ended output voltage.
V4 measures the differential input voltage.
I1 measures the bias current.
40. Calculate the voltage across each collector resistor:
VR C1 = (1.35 mA)(5.1 kΩ) = 6.89 V
VR C 2 = (1.29 mA)(5.1 kΩ) = 6.58 V
The differential output voltage is:
VOUT VC(Q 2) VC(Q1) (VCC VR C2 ) (VCC VR C1 ) VR C1 VR C2
= 6.89 V – 6.58 V = 0.31 V = 310 mV
41. (a) Single-ended differential input, differential output
(b) Single-ended, differential input, single-ended output
(c) Double-ended differential input, single-ended output
(d) Double-ended differential input, differential output
Chapter 6
Section 6-8 Troubleshooting
R1 10 k
42. VE 10 V 0.7 V 10 V 0.7 V 1.05 V
R1 R2 57 k
VE 1.05 V
IE 1.05 mA
R4 1.0 k
VC = 10 V – (1.05 mA)(4.7 kΩ) = 5.07 V
VCE = 5.07 V – 1.05 V = 4.02 V
VCE 4.02 V
rCE 3.83 k
I E 1.05 mA
With C2 shorted:
RIN(2) R6 DC R8 10 k 125(1.0 k) 9.26 k
Looking from the collector of Q1:
R4 ) RIN(2) (3.83 k 1.0 k) 9.26 k 3.17 k
(rCE
3.17 k
VC1 10 V 4.03 V
3.17 k 4.7 k
43. Q1 is in cutoff. IC = 0 A, so VC2 = 10 V.
44. (a) Reduced gain
(b) No output signal
(c) Reduced gain
(d) Bias levels of first stage will change. IC will increase and Q1 will go into saturation.
(e) No signal at the Q1 collector
(f) Signal at the Q2 base. No output signal.
45. re 10.9 Rin = 1.48 kΩ
Av1 = 93.6 Av2 = 302
Test Point DC Volts AC Volts (rms)
Input 0V 25 μA
Q1 base 2.99 V 20.8 μV
Q1 emitter 2.29 V 0V
Q1 collector 7.44 V 1.95 mV
Q2 base 2.99 V 1.95 mV
Q2 emitter 2.29 V 0V
Q2 collector 7.44 V 589 mV
Output 0V 589 mV
Chapter 6
Device Application Problems
46. For the block diagram of textbook Figure 6-47 with no output from the power amplifier
or preamplifier and only one faulty block, the power amplifier must be ok because the
fault must be one that affects the preamplifier’s output prior to the power amplifier.
Check the input to the preamplifier.
47. (a) No output signal
(b) Reduced output signal
(c) No output signal
(d) Reduced output signal
(e) No output signal
(f) Increased output signal (perhaps with distortion)
48. R7 = 220 Ω will bias Q2 off.
49. (a) Q1 is in cutoff.
(b) VC1 = VEE
(c) VC2 is unchanged and at 5.87 V.
Datasheet Problems
50. From the datasheet in textbook Figure 6-64:
(a) For a 2N3947, ac (min) h fe (min) 100
(b) For a 2N3947, re(min) cannot be determined since hre(min) is not given.
(c) For a 2N3947, rc(min) cannot be determined since hre(min) is not given.
51. From the 2N3947 datasheet in Figure 6-64:
(a) For a 2N3947, ac (max) 700
hre 20 104
(b) For a 2N3947, re(max) 40
hoe 50 S
hre 1 20 10 4 1
(c) For a 2N3947, re(max) 20k
hoe 50 S
52. For maximum current gain, a 2N3947 should be used.
Chapter 6
Advanced Problems
53. In the circuit of textbook Figure 6-63, a leaky coupling capacitor would affect the biasing
of the transistors, attenuate the ac signal, and decrease the frequency response.
54. See Figure 6-3.
Figure 6-3
55. For the 2nd stage:
30 V 30 V
I R 6 7 435 A
R6 R7 69 k
VB2 VCC I R6-7 R6 15 V (435 k)
15 V 20.5 V 5.5 V
VE2 5.5 V 0.7 V
I E2 1.21 mA
R9 R10 5.13 k
25 mA
re2 20.7
1.21 mA
Chapter 6
With R10 = 0 Ω for max gain:
R8 6.8 k
Av(2) 45.1 (unloaded)
R9 re2 150.7
With a 10 kΩ load:
R8 RL 6.8 k 10 k 4.05 k
Av(2) 26.9
R9 re2 150.7 150.7
To keep unloaded gain:
4.05 k
45.1
R9 20.7
4.05 kΩ = 45.1(R9 + 20.7 Ω) = 45.1R9 + 934 Ω
4.05 k 934
R9 69.1
45.1
56. RC > (100)(330 Ω) = 33 kΩ
To prevent cutoff, VC must be no greater than
12 V – (100)(1.414)(25 mV) = 8.46 V
In addition, VC must fall no lower than 8.46 V – 3.54 V = 4.93 V to prevent saturation.
RC 100( RE re)
25 mV
re
IE
12 V – ICRC = 8.46 V
ICRC = 3.54 V
I C (100( RE re)) 3.54 V
25 mV
I C 100 330 3.54 V
I C
(33 kΩ)IC + 2.5 V = 3.54 V
IC = 31.4 μA
25 mV
re 797
31.4 A
RC = 100(330 Ω + 797 Ω) = 113 kΩ
Let RC = 120 kΩ.
VC = 12 V – (31.4 μA)(120 kΩ) = 8.23 V
VC(sat) = 8.23 V – 3.54 V = 4.69 V
Chapter 6
RE(tot) 4.69 V
RC 7.31 V
RE(tot) = (0.642)(120 kΩ) = 77 kΩ. Let RE = 68 kΩ.
VE = (31.4 μA)(68 kΩ) = 2.14 V
VB = 2.14 V + 0.7 V = 2.84 V
R2 2.84 V
0.310
R1 9.16 V
R2 = 0.310R1. If R1 = 20 kΩ, R2 = 6.2 kΩ.
The amplifier circuit is shown in Figure 6-4.
From the design:
6.2 k
VB 12 V 2.84 V
26.2 k
VE = 2.14 V
2.14 V
IC IE 31.3 A
68.3 k
25 mV
re 798
31.3 A
120 k
Av 106 or 40.5 dB
795 330
VC = 12 V – (31.3 μA)(120 kΩ) = 8.24 V
The design is a close fit.
Figure 6-4
Chapter 6
57. See Figure 6-5.
Rin 120 k 120 k (100)(5.1 k) 53.6 k minimum
Figure 6-5
58. See Figure 6-6.
Figure 6-6
59. See Figure 6-7.
6 V 0.7 V
IC 10 mA
510 2 k /100
25 mA
re 2.5
10 mA
180
Av 72.4
2.5
This is reasonably close (≈3.3% off)
and can be made closer by putting a
7.5 Ω resistor in series with the
180 Ω collector resistor.
Figure 6-7
Chapter 6
60. Assuming βac = 200,
1 1
C1
2 f c R 2 (100 Hz)(330 k 330 k (200 34 k))
1
0.01 F
2 (100 Hz)(161 k)
1 1
C2
2 f c R 2 (100 Hz)(22 k 47 k 22 k (200 5.13 k))
1
0.043 F
2 (100 Hz)(36.98 k)
61. IC IE
RC RC RC R I VR C
Av C C 40 VR C
re 25 mV/I E 25 mV/I C 25 mV 25 mV
Multisim Troubleshooting Problems
62. C2 open
63. C2 shorted
64. RE leaky
65. C1 open
66. C2 open
67. C3 open
Chapter 7
BJT Power Amplifiers
Section 7-1 The Class A Power Amplifier
R2 330
1. (a) VB VCC 15 V 3.72 V
R1 R2 1.0 k 330 k
VE VB VBE 3.72 0.7 V 3.02 V
VE 3.02 V
I CQ I E 68.4 mA
RE1 RE2 8.2 36
VCEQ VCC ( I C )( RE1 RE2 RL ) 15 V (68.4 mA)(8.2 36 100 )
5.14 V
RL 100
(b) Av 11.7
RE1 re 8.2 0.3
Rin ac ( RE1 re ) R1 R2
100(8.2 0.37 ) 330 1.0 k 192
R 192
Ap Av2 in 11.7 2 263
RL 100
The computed voltage and power gains are slightly higher if re is ignored.
2. (a) If RL is removed, there is no collector current; hence, the power dissipated in the
transistor is zero.
(b) Power is dissipated only in the bias resistors plus a small amount in RE1 and RE2.
Since the load resistor has been removed, the base voltage is altered. The base
voltage can be found from the Thevenin equivalent drawn for the bias circuit in
Figure 7-1.
Figure 7-1
Chapter 7
Applying the voltage-divider rule and including the base-emitter diode drop of 0.7
V result in a base voltage of 1.2 V. The power supply current is then computed as
VCC 1.2 V 15 V 1.2 V
I CC 13.8 mA
R1 1.0 k
Power from the supply is then computed as
PT I CCVCC (13.8 mA)(15 V) 207 mW
(c) Av 11.7 (see problem 1(b)). Vin 500 mVpp 177 mVrms .
Vout AvVin (11.7)(177 mV) 2.07 V
2
Vout 2.07 V 2
Pout 42.8 mW
RL 100
3. The changes are shown in Figure 7-2. The advantage of this arrangement is that the load
resistor is referenced to ground.
Figure 7-2
4. A CC amplifier has a voltage gain of approximately 1. Therefore,
R 2.2 k
Ap in 44
Rout 50
R2 510
5. (a) VTH VCC 12 V 5.14 V
R1 R2 1190
R R (680 )(510 )
RTH 1 2 291
R1 R2 1190
VTH VBE 5.14 V 0.7 V
IE 54 mA
RE RTH / DC 79.7 291 /125
I C I E 54 mA
Chapter 7
VC VCC I C RC 12 V (54 mA)(100 ) = 6.6 V
VE I E RE (54 mA)(79.7 ) 4.3 V
VCE VC VE 6.6 V 4.3 V 2.3 V
R2 4.7 k
(b) VTH VCC 12 V 3.38 V
R1 R2 16.7 k
R R (12 k)(4.7 k)
RTH 1 2 3.38 k
R1 R2 16.7 k
VTH VBE 3.38 V 0.7 V
IE 15.7 mA
RE RTH / DC 142 3.38 k / 120
I C I E 15.7 mA
VC VCC I C RC 12 V (15.7 mA)(470 ) 4.62 V
VE I E RE (15.7 mA)(142 ) 2.23 V
VCE VC VE 4.62 V 2.23 V 2.39 V
6. The Q-point does not change because RL is capacitively coupled and does not affect the
DC values.
7. For the circuit in Figure 7-42(a):
From Problem 5(a),
I CQ 54 mA; VCEQ 2.3 V
Re RC RL 100 100 50
Vce( cutoff ) VCEQ I CQ Rc 2.3 V (54 mA(50 ) 5 V
Since VCEQ is closer to saturation, Ic is limited to
VCEQ 2.3 V
Ic( p) 46 mA
Rc 50
Vout is limited to
Vout ( p ) VCEQ 2.3 V
For the circuit in Figure 7-43(b):
From Problem 5(b),
I CQ 15.7 mA; VCEQ 2.39 V
Re RC RL 470 470 235
Vce ( cutoff ) VCEQ I CQ Rc 2.39 V (15.7 mA)(235 ) 6.08 V
Chapter 7
Since VCEQ is closer to saturation, Ic is limited to
VCEQ 2.39 V
Ic( p) 10.2 mA
Rc 235
Vout is limited to
Vout( p ) VCEQ 2.39 V
R
8. (a) Ap Av2 in
RL
Rc R RL 100 100 50
Av C 10.6
RE1 RE1 4.7 4.7
Rin R1 R2 Rin (base ) R1 R2 ac RE1
Rin 680 510 (125)(4.7 ) 680 510 588 195
195
Ap (10.6) 2 219
100
Rc R RL 470 470 235
(b) Av C 10.7
RE1 RE1 22 22
Rin 12 k 4.7 k (120)(22 ) 12 k 4.7 k 2.64 k 1.48 k
1.48 k
Ap (10.7) 2 361
470
R2 DC ( RE1 RE2 )VCC
9. VB
(R1 R2 DC ( RE1 RE2 )
1.0 k 100(130 k) 24 V
4.7 k 1 k 100(130 k 4.2 V
VE VB 0.7 V 4.2 0.7 V 3.5 V
I C I E VE 3.5 V
26.9 mA
( RE1 RE2 ) 130
VC VCC I CRC 24 V (26.9 mA)(560 ) 8.94 V
VCE VC VE 8.94 V 3.5 V 5.44 V
RC 560
10. Av 28
re RE1 20
Chapter 7
R2 1 k
11. VTH VCC 24 V 4.2 V
R1 R2 5.7 k
R1R2 (4.7 k)(1 k)
RTH 825
R1 R2 5.7 k
VTH VBE 4.2 V 0.7 V
IE 25 mA
RE RTH / DC 130 825 / 90
I C I E 25 mA
VC VCC I C RC 24 V (25 mA)(560 ) 10 V
VE I E RE (25 mA)(130 ) 3.25 V
VCEQ VC VE 10 V 3.25 V 6.75 V
PD(min) PDQ I CQVCEQ (25 mA)(6.75 V) 169 mW
12. From Problem 9: I CQ 25 mA and VCEQ 6.75 V
Vce ( cutoff ) VCEQ I CQ Rc 6.75 V (25 mA)(264 ) 13.5 V
2
Pout 0.5 I CQ Rc 0.5(25 mA) 2 (264 ) 82.5 mW
Pout P P 82.5 mW
out out 0.138
PDC VCC I CC VCC I CQ (24 V)(25 mA)
Section 7-2 The Class B and Class AB Push-Pull Amplifiers
13. (a) VB(Q1) 0 V 0.7 V 0.7 V
VB(Q 2) 0 V 0.7 V 0.7 V
VCC (VCC ) 1.4 V 9 V (9 V) 1.4 V
I CQ 8.3 mA
R1 R2 1.0 k 1.0 k
VCEQ(Q1) 9 V
VCEQ(Q 2) 9 V
(b) Vout Vin 5.0 V rms
(Vout ) 2 5.0 V 2
Pout 0.5 W
RL 50
Chapter 7
VCC 9.0 V
14. I c ( sat ) 180 mA
RL 50
Vce (cutoff ) 9 V
These points define the ac load line as shown in Figure 7-3. The Q-point is at a collector
current of 8.3 mA (see problem 13) and the dc load line rises vertically through this point.
Figure 7-3
15. Rin ac (re RL ) R1 R2
From Problem 11,
I CQ 8.3 mA
so, I E 8.3 mA
25 mV
re 3
8.3 mA
Rin 100(53 1.0 k 1.0 k
5300 1.0 k 1.0 k 457 Ω
16. The DC voltage at the output becomes negative instead of 0 V.
17. (a) VB(Q1) 7.5 V 0.7 V 8.2 V
VB(Q 2) 7.5 V 0.7 V 6.8 V
15 V
VE 7.5 V
2
VCC 1.4 V 15 V 1.4 V
I CQ 6.8 mA
R1 R2 1.0 k+1.0 k
VCEQ(Q1) 15 V 7.5 V 7.5 V
VCEQ(Q 2) 0 V 7.5 V 7.5 V
Chapter 7
(b) Vin Vout 10 Vpp 3.54 V rms
(VL ) 2 (3.54 V) 2
PL 167 mW
RL 75
18. (a) Maximum peak voltage = 7.5 Vp. 7.5 Vp 5.30 V rms
(VL ) 2 (5.30 V) 2
PL(max) 375 mW
RL 75
(b) Maximum peak voltage = 12 Vp. 12 Vp = 8.48 V rms
(VL ) 2 (8.48 V) 2
PL(max) 960 mW
RL 75
19. (a) C2 open or Q2 open
(b) power supply off, open R1, Q1 base shorted to ground
(c) Q1 has collector-to-emitter short
(d) one or both diodes shorted
20. Rin ac (re RL ) R1 R2
From Problem 15:
ICQ = 6.8 mA
I E 6.8 mA
25 mV 25 mV
re 3.68
IE 6.8 mA
Rin 200(78.7 ) 1 k 1 k 485
485
Vb 1 V 0.91 V rms
485 50
Section 7-3 The Class C Amplifier
t
21. PD(avg) on VCE(sat) I C(sat) (0.1)(0.18 V)(25 mA) 450 μW
T
1 1
22. fr 50.3 kHz
2 LC 2 (10 mH) (0.001 F)
23. Vout ( pp ) 2 VCC 2(12 V) 24 V
Chapter 7
2
0.5 VCC 0.5(15 V) 2
24. Pout 2.25 W
Rc 50
t
PD(avg) on VCE(sat) I C(sat) (0.1)(0.18 V)(25 mA) 0.45 mW
T
Pout 2.25 W
0.9998
Pout PD(avg) 2.25 W 0.45 mW
Section 7-4 Troubleshooting
25. With C1 open, only the negative half of the input signal appears across RL.
26. One of the transistors is open between the collector and emitter or a coupling capacitor is
open.
27. (a) No dc supply voltage or R1 open
(b) Diode D2 open
(c) Circuit is OK
(d) Q1 shorted from collector to emitter
Device Application Problems
28. For the block diagram of textbook Figure 7-33 with no signal from the power amplifier or
preamplifier, but with the microphone working, the problem is in the power amplifier or
preamplifier. It must be assumed that the preamp is faulty, causing the power amp to
have no signal.
29. For the circuit of Figure 7-34 with the base-emitter junction of Q2 open, the dc output
will be approximately –15 V with a signal output approximately equal to the input.
30. For the circuit of text Figure 7-34 with the collector-emitter junction of Q5 open, the dc
output will be approximately +15 V with a signal output approximately equal to the input
(some distortion possible).
31. On the circuit board of text Figure 7-48, the vertically oriented diode has been installed
backwards.
Datasheet Problems
32. From the BD135 datasheet of textbook Figure 7-49:
(a) DC(min) 40 @ I C 150 mA, VCE 2 V
DC(min) 25 @ I C 5 mA, VCE 2 V
(b) For a BD135, VCE(max) VCEO 45 V
(c) PD(max) 12.5 W @ TC 25C
(d) I C(max) 1.5 A
Chapter 7
33. PD = 10 W @ 50ºC from graph in Figure 7-49.
34. PD = 1 W @ 50ºC. Extrapolating from the case temperature graph in text Figure 7-49,
since PD = 1.25 W @ 25ºC ambient. This derating gives 1 W.
35. As IC increases from 10 mA to approximately 125 mA, the dc current gain increases. As
IC increases above approximately 125 mA, the dc current gain decreases.
36. hFE 89 @ I C 20 mA
Advanced Problems
37. TC is much closer to the actual junction temperature than TA. In a given operating
environment, TA is always less than TC.
24 V 24 V
38. I C(sat) 55.8 mA
330 100 430
VCE(cutoff) = 24 V
1.0 k
VBQ 24 V 4.21 V
1.0 k 4.7 k
VEQ = 4.21 V – 0.7 V = 3.51 V
3.51 V
I EQ I CQ 35.1 mA
100
Rc 330 330 165
VCQ = 24 V – (35.1 mA)(330 Ω) = 12.4 V
VCEQ = 12.4 V – 3.51 V = 8.90 V
8.90 V
I c (sat) 35.1 mA 89.1 mA
165
Vce(cutoff) = 8.90 V + (35.1 mA)(165 Ω) = 14.7 V
See Figure 7-4.
Figure 7-4
Chapter 7
39. See Figure 7-5.
15 V
I R1 I R 2 174 mA
86
18
VB 15 V 3.14 V
86
VE = 3.14 V – 0.7 V = 2.44 V
2.44 V
IE IC 503 mA
4.85
VC = 15 V – (10 Ω)(503 mA) = 9.97 V
VCE = 7.53 V
25 mV
re 0.05
503 mA
The ac resistance affecting the load line is
Rc Re re 10
Figure 7-5
ac DC 100
7.53 V
I c ( sat ) 503 mA 1.24 A
10.2
Vce(cutoff) = 7.53 V + (503 mA)(10.2 Ω) = 12.7 V
The Q-point is closer to cutoff so
Pout = (0.5)(503 mA)2(10.2 Ω) = 1.29 W
As loading occurs, the Q-point will still be closer to cutoff. The circuit will have
Pout ≥ 1 W for RL ≥ 37.7 Ω. (39 Ω standard)
Chapter 7
40. Preamp quiescent current:
30 V
I1 I 2 45 A
660 k
15 V 0.7 V
I3 I 4 I5 421 A
34 k
30 V
I6 I7 435 A
69 k
VB2 = 15 V – (435 μA)(47 kΩ) = –5.45 V
15 V (5.45 V 0.7 V)
I8 I 9 I10 1.73 mA
5.13 k
Itot = 45 μA + 421 μA + 435 μA + 1.73 mA = 2.63 mA
Power amp quiescent current:
I11 0
15.7 V 3(0.7 V) 13.6 V
I12 13.6 mA
1.0 k 1.0 k
15 V (0.7 V) 14.3 V
I13 65 mA
220 220
Itot = 13.6 mA + 65 mA = 78.6 mA
Signal current to load:
Scope shows ≈ 9.8 V peak output.
0.707(9.8 V)
IL 866 mA
8
Itot(sys) = 2.63 mA + 78.6 mA + 866 mA = 947 mA
Amp. hrs = 947 mA 4 hrs = 3.79 Ah
Multisim Troubleshooting Problems
41. Cin open
42. RE2 open
43. Q1 collector-emitter open
44. D2 shorted
45. Q2 drain-source open
Chapter 8
Field-Effect Transistors (FETs)
Section 8-1 The JFET
1. (a) A greater VGS narrows the depletion region.
(b) The channel resistance increases with increased VGS.
2. The gate-to-source voltage of an n-channel JFET must be zero or negative in order to
maintain the required reverse-bias condition.
3. See Figure 8-1.
Figure 8-1
4. See Figure 8-2.
Figure 8-2
Chapter 8
Section 8-2 JFET Characteristics and Parameters
5. VDS = VP = 5 V at point where ID becomes constant.
6. VGS(off) = –VP = –6 V
The device is on, because VGS = –2 V.
7. By definition, ID = IDSS when VGS = 0 V for values of VDS > VP.
Therefore, ID = 10 mA.
8. Since VGS > VGS(off), the JFET is off and ID = 0 A.
9. VP = –VGS(off) = – (– 4 V) = 4 V
The voltmeter reads VDS. As VDD is increased, VDS also increases. The point at which ID
reaches a constant value is VDS = VP = 4 V.
2
V
10. I D I DSS 1 GS
VGS(off)
2
0V
I D 5 mA 1 5 mA
8 V
2
1 V
I D 5 mA 1 3.83 mA
8 V
2
2 V
I D 5 mA 1 2.81 mA
8 V
2
3 V
I D 5 mA 1 1.95 mA
8 V
2
4 V
I D 5 mA 1 1.25 mA
8 V
2
5 V
I D 5 mA 1 0.703 mA
8 V
2
6 V
I D 5 mA 1 0.313 mA
8 V
2
7 V
I D 5 mA 1 0.078 mA
8 V
2
8 V
I D 5 mA 1 0 mA
8 V
Chapter 8
See Figure 8-3.
Figure 8-3
2
V
11. I D I DSS 1 GS
VGS(off)
VGS ID
1
VGS(off) I DSS
VGS ID
1
VGS(off) I DSS
ID
VGS VGS(off) 1
I DSS
2.25 mA
VGS 8 V 1 8 V(0.329) 2.63 V
5 mA
V 4V
12. g m g m 0 1 GS 3200 S 1 1600 S
VGS(off) 8V
V 2V
13. g m g m 0 1 GS 2000 S 1 1429 S
VGS(off) 7 V
gfs = gm = 1429 μS
VGS 10V
14. RIN 2000 M
I GSS 5 nA
Chapter 8
2
V
15. VGS 0 V: I D I DSS 1 GS 8 mA(1 0) 2 8 mA
VGS(off)
2
1 V 2 2
VGS 1 V: I D 8 mA 1 8 mA(1 0.2) 8 mA(0.8) 5.12 mA
5 V
2
2 V 2 2
VGS 2 V: I D 8 mA 1 8 mA(1 0.4) 8 mA(0.6) 2.88 mA
5 V
2
3 V 2 2
VGS 3 V: I D 8 mA 1 8 mA(1 0.6) 8 mA(0.4) 1.28 mA
5 V
2
4 V 2 2
VGS 4 V: I D 8 mA 1 8 mA(1 0.8) 8 mA(0.2) 0.320 mA
5 V
2
5 V 2 2
VGS 5 V: I D 8 mA 1 8 mA(1 1) 8 mA(0) 0 mA
5 V
Section 8-3 JFET Biasing
16. See Figure 8-4.
Figure 8-4
Chapter 8
17. See Figure 8-5.
(a)
Figure 8-5a
(b)
Figure 8-5b
18. VGS = –IDRS = –(12 mA)(100 Ω) = –1.2 V
VGS 4 V
19. RS 800
ID 5 mA
VGS 3 V
20. RS 1.2 k
ID 2.5 mA
Chapter 8
21. (a) ID = IDSS = 20 mA
(b) ID = 0 A
(c) ID increases
22. (a) VS = (1 mA)(1.0 kΩ) = 1 V
VD = 12 V – (1 mA)(4.7 kΩ) = 7.3 V
VG = 0 V
VGS = VG – VS = 0 V – 1 V = –1 V
VDS = 7.3 V – 1 V = 6.3 V
(b) VS = (5 mA)(100 Ω) = 0.5 V
VD = 9 V – (5 mA)(470 Ω) = 6.65 V
VG = 0 V
VGS = VG – VS = 0 V – 0.5 V = –0.5 V
VDS = 6.65 V – 0.5 V = 6.15 V
(c) VS = (–3 mA)(470 Ω) = –1.41 V
VD = –15 V – (3 mA)(2.2 kΩ) = –8.4 V
VG = 0 V
VGS = VG – VS = 0 V – (–1.41 V) = 1.41 V
VDS = –8.4 V – (– 1.41 V) = – 6.99 V
23. From the graph, VGS 2 V at ID = 9.5 mA.
VGS 2 V
RS 211
ID 9.5 mA
I DSS 14 mA
24. ID 7 mA
2 2
VGS(off) 10 V
VGS 2.93 V
3.414 3.414
VGS 2.93 V
RS 419 (The nearest standard value is 430 Ω.)
ID 7 mA
VDD VD 24 V 12 V
RD 1.7 k (The nearest standard value is 1.8 kΩ.)
ID 7 mA
Chapter 8
Select RG = 1.0 MΩ. See Figure 8-6.
Figure 8-6
25. RIN(total) RG RIN
VGS 10 V
RIN 500 M
I GSS 20 nA
RIN(total) 10 MΩ 500 MΩ 9.8 MΩ
26. For I D 0,
VGS I D RS (0)(330 ) 0 V
For I D I DSS 5 mA
VGS I D RS (5 mA)(330 ) 1.65 V
From the graph in Figure 8-69 in the textbook, the Q-point is
VGS 0.95 V and I D 2.9 mA
27. For I D 0,
VGS 0 V
For I D I DSS 10 mA,
VGS I D RS (10 mA)(390 ) 3.9 V
From the graph in Figure 8-70 in the textbook, the Q-point is
VGS 2.1 V and I D 5.3 mA
28. Since VR D 9 V 5 V 4 V
VR D 4V
ID 0.85 mA
RD 4.7 k
VS I D RS (0.85 mA)(3.3 k) 2.81 V
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Chapter 8
R2 2.2 M
VG VDD 9 V 1.62 V
R1 R2 12.2 M
VGS VG VS 1.62 V 2.81 V 1.19 V
Q-point: I D 0.85 mA , VGS 1.19 V
29. For I D 0,
R2 2.2 M
VGS VG VDD 12 V 4.8 V
R1 R2 5.5 M
For VGS 0 V, VS 4.8 V
VS VG VGS 4.8 V
ID 1.45 mA
RS RS 3.3 k
The Q-point is taken from the graph in Figure 8-75 in the textbook.
I D 1.9 mA , VGS 1.5 V
Section 8-4 The Ohmic Region
VDS 0.8 V
30. RDS 4 k
I D 0.20 mA
0.4 V
31. RDS1 2.67 k
0.15 mA
0.6 V
RDS2 1.33k
0.45 mA
RDS 2.67 k 1.33k 1.34 k
V 1V
32. g m g m 0 1 GS 1.5 mS 1
3.5V
VGS(off)
= 1.5 mS(0.714) = 1.07 mS
1 1
33. rds 935
g m 1.07 mS
Chapter 8
Section 8-5 The MOSFET
34. See Figure 8-7.
Figure 8-7
35. An n-channel D-MOSFET with a positive VGS is operating in the enhancement mode.
36. An E-MOSFET has no physical channel or depletion mode. A D-MOSFET has a physical
channel and can be operated in either depletion or enhancement modes.
37. MOSFETs have a very high input resistance because the gate is insulated from the
channel by an SiO2 layer.
Section 8-6 MOSFET Characteristics and Parameters
I D(on) 10 mA
38. K 0.12 mA/V 2
VGS VGS(th)
2
( 12 V 3 V) 2
2
I D K VGS VGS(off) (0.12 mA/V 2 )( 6 V 3 V) 2 1.08 mA
2
V
39. I D I DSS 1 GS
VGS(off)
ID 3 mA
I DSS 2
2
4.69 mA
V 2 V
1 GS 1
10 V
VGS(off)
40. (a) n channel
2
V 2
5 V
(b) I D I DSS 1 GS I D 8 mA 1 0 mA
VGS(off) 5 V
2 2
4 V 3 V
I D 8 mA 1 0.32 mA I D 8 mA 1 1.28 mA
5 V 5 V
2 2
2 V 1 V
I D 8 mA 1 2.88 mA I D 8 mA 1 5.12 mA
5 V 5 V
Chapter 8
2 2
0V 1V
I D 8 mA 1 8 mA I D 8 mA 1 11.5 mA
5 V 5 V
2 2
2V 3V
I D 8 mA 1 15.7 mA I D 8 mA 1 20.5 mA
5 V 5 V
2 2
4V 5V
I D 8 mA 1 25.9 mA I D 8 mA 1 32 mA
5 V 5 V
(c) See Figure 8-8.
Figure 8-8
Section 8-7 MOSFET Biasing
41. (a) Depletion
(b) Enhancement
(c) Zero bias
(d) Depletion
10 M
42. (a) VGS 10 V 6.8 V This MOSFET is on.
14.7 M
1.0 M
(b) VGS (25 V) 2.27 V This MOSFET is off.
11 M
43. Since VGS 0 V for each circuit, I D I DSS =8 mA .
(a) VDS VDD I D RD =12 V (8 mA)(1.0 k) 4 V
(b) VDS VDD I D RD =15 V (8 mA)(1.2 k) 5.4 V
(c) VDS VDD I D RD = 9 V (8 mA)(560 ) 4.52 V
Chapter 8
44. (a) I D(on) 3mA @ 4 V, VGS(th) =2 V
R2 4.7 M
VGS VDD 10 V 3.2 V
R1 R2 14.7 M
I D(on) 3 mA 3 mA
K 0.75 mA/V 2
VGS VGS(th)
2 2
(4 V 2 V) (2 V) 2
2
I D K VGS VGS(th) (0.75 mA/V 2 )(3.2 V 2 V) 2 1.08 mA
VDS VDD I D RD 10V (1.08 mA)(1.0 k) 10 V 1.08 V 8.92 V
(b) I D(on) 2 mA @ 3 V, VGS(th) =1.5 V
R2 10 M
VGS VDD 5V 2.5 V
R1 R2 20 M
I D(on) 2 mA 2 mA
K 0.89 mA/V 2
VGS VGS(th)
2 2
(3 V 1.5 V) (1.5V) 2
2
I D K VGS VGS(th) (0.89 mA/V 2 )(2.5 V 1.5 V) 2 0.89 mA
VDS VDD I D RD 5V (0.89 mA)(1.5 k) 5 V 1.34 V 3.66 V
45. (a) VDS VGS 5 V
VDD VDS 12 V 5 V
ID 3.18 mA
RD 2.2 k
(b) VDS VGS 3.2 V
VDD VDS 8 V 3.2 V
ID 1.02 mA
RD 4.7 k
46. VDS VDD I D RD 15V (1 mA)(8.2 k) 6.8 V
VGS VDS I G RG 6.8V (50 pA)(22 M) 6.799 V
Section 8-8 The IGBT
47. The input resistance of an IGBT is very high because of the insulated gate structure.
48. With excessive collector current, the parasitic transistor turns on and the IGBT acts as a
thyristor.
Chapter 8
Section 8-9 Troubleshooting
49. When ID goes to zero, the possible faults are:
RD or RS open, JFET drain-to-source open, no supply voltage, or ground connection open.
50. If ID goes to 16 mA, the possible faults are:
The JFET is shorted from drain-to-source or VDD has increased.
51. If VDD is changed to –20 V, ID will change very little or none because the device is
operating in the constant-current region of the characteristic curve.
52. The device is off. The gate bias voltage must be less than VGS(th). The gate could be
shorted or partially shorted to ground.
53. The device is saturated, so there is very little voltage from drain-to-source. This indicates
that VGS is too high. The 1.0 MΩ bias resistor is probably open.
Device Application Problems
54. (a) –500 mV
(b) –200 mV
(c) 0 mV
(d) 400 mV
55. At VG2S 6 V, I D 10 mA
At VG2S 1 V, I D 5 mA
56. VG1S Vsensor 400 mV
VOUT = 9.048 V
VDD VOUT 12 V 9.048 V
ID 2.64 mA
R3 R4 1120
VG1S Vsensor 300 mV
VOUT = 7.574 V
12 V 7.574 V
ID 3.95 mA
1120
VG1S Vsensor 200 mV
VOUT = 5.930 V
12 V 5.930 V
ID 5.42 mA
1120
VG1S Vsensor 100 mV
Chapter 8
VOUT = 4.890 V
12 V 4.890 V
ID 6.35 mA
1120
VG1S Vsensor 0 mV
VOUT = 4.197 V
12 V 4.197 V
ID 6.97 mA
1120
VG1S Vsensor 100 mV
VOUT = 3.562 V
12 V 3.562 V
ID 7.35 mA
1120
VG1S Vsensor 200 mV
VOUT = 2.960 V
12 V 2.960 V
ID 8.07 mA
1120
VG1S Vsensor 300 mV
VOUT = 2.382 V
12 V 2.382 V
ID 8.59 mA
1120
See Figure 8-9.
Figure 8-9
Chapter 8
R2 50 k
57. VG2S VDD 12 V 4 V
R1 R2 150 k
From the graph in Figure 8-82 in the textbook for VG1S = 0 and VG2S = 4 V:
I D 8 mA
VOUT 12 V (8 mA)(1120 ) 3.04 V
Datasheet Problems
58. The 2N5457 is an n-channel JFET.
59. From the datasheet in textbook Figure 8-14:
(a) For a 2N5457, VGS(off) 0.5 V minimum
(b) For a 2N5457, VDS(max) 25 V
(c) For a 2N5458 @ 25°C, PD(max) 310 mW
(d) For a 2N5459, VGS(rev) 25 V maximum
60. PD(max) 310 mW (2.82 mW/ C)(65C 25C) 310 mW 113 mW 197 mW
61. g m0(min) g fs 2000 S
62. Typical I D I DSS 9 mA
63. From the datasheet graph in textbook Figure 8-80:
I D 1.4 mA at VGS = 0
64. For a 2N3796 with VGS 6 V , I D 15 mA
65. From the datasheet graph in textbook Figure 8-83:
At VGS 3 V , I D 13 mA
At VGS 2 V , I D 0.4 mA
66. y fs 1500 S at f = 1 kHz and at f = 1 MHz for both the 2N3796 and 2N3797. There is
no change in gfs over the frequency range.
67. For a 2N3796, VGS(off) = –3.0 V typical
Chapter 8
Advanced Problems
68. For the circuit of textbook Figure 8-84:
2
V
I D I DSS 1 GS where VGS I D RS
VGS(off)
From the 2N5457 datasheet:
IDSS(min) = 1.0 mA and VGS(off) = –0.5 V minimum
I D 66.3 A
VGS (66.3 A)(5.6 k) 0.371 V
VDS 12 V (66.3 A)(10 k 5.6k) 11.0 V
69. For the circuit of textbook Figure 8-85:
3.3 k
VC 9 V (0.248)(9 V) 2.23V
13.3 k
From the equation,
2
VGS
I D I DSS where VGS VG I D RS
1 VGS(off)
ID is maximum for IDSS(max) and VGS(off) max, so that
IDSS = 16 mA and VGS(off) = –8.0 V
ID = 3.58 mA
VGS 2.23 V (3.58 mA)(1.8 k) 2.23 V 6.45 V 4.21 V
70. From the 2N5457 datasheet:
I DSS(min) 1.0 mA and VGS(off ) 0.5 minimum
I D(min) 66.3 A
VDS(max) 12 V (66.3 A)(15.6 k) 11.0 V
and
I DSS(max) 5.0 mA and VGS(off) 6.0 maximum
I D(max) 677 A
VDS(min) 12 V (677 A)(15.6 k) 1.4 V
Chapter 8
71. VpH 300 mV
I D (2.9 mA)(1 0.3 V/5.0 V) 2 (2.9 mA)(1.06) 2 3.26 mA
VDS 15 V (3.26 mA)(2.76 k) 15 V 8.99 V 6.01 V
2
(1 mA)RS
72. 1 mA I DSS 1
VGS(off)
2
(1 mA)RS
1 mA 2.9 mA 1
0.5V
2
(1 mA)RS
0.345 1
0.5V
(1 mA)RS
0.587 1
0.5V
(1 mA)RS
0.413
0.5V
RS = 2.06 kΩ
Use RS = 2.2 kΩ.
Then ID = 963 μA
VGS VS (963 A)(2.2k) 2.19 V
So, VD = 2.19 V + 4.5 V = 6.62 V
9 V 6.62 V
RD 2.47 k
963 A
Use RD = 2.4 kΩ.
So, VDS 9 V (963 A)(4.6k) 4.57 V
73. Let ID = 20 mA.
4V
RD 200
20 mA
Let VS = 2 V.
2V
RS 100
20 mA
I D(on) 500 mA
K 6.17 mA/V 2
(VGS(on) VGS(th) ) 2
(10 V 1V)
Let ID = 20 mA.
Chapter 8
VGS 1 V 1.8 V
VGS 2.8 V
VG VS 2.8 V 4.8 V
Figure 8-8
For the voltage divider:
R1 7.2 V
1.5
R2 4.8V
Let R2 = 10 kΩ.
R1 = (1.5)(10 kΩ) = 15 kΩ
See Figure 8-10.
Multisim Troubleshooting Problems
74. RS shorted
75. RD shorted
76. RG shorted
77. R1 open
78. Drain-source open
79. RD open
80. R2 shorted
81. Drain-source shorted
82. R1 shorted
Chapter 9
FET Amplifiers and
Switching Circuits
Section 9-1 The Common-Source Amplifier
1. Two general approaches for analyzing a JFET circuit are dc analysis and ac analysis.
2. Av g m Rd (5 mS)(2.2 kΩ) 11
3. (a) I d g mVgs (6000 S)(10 mV) 60 A
(b) I d g mVgs (6000 S)(150 mV) 900 μA
(c) I d g mVgs (6000 S)(0.6 V) 3.6 mA
(d) I d g mVgs (6000 S)(1 V) 6 mA
4. Av g m Rd
Av 20
Rd 5.71 kΩ
g m 3500 S
R r (4.7 k)(12 k)
5. Av D ds g m 4.2 mS 14.2
RD rds 16.7 k
6. Rd RD rds 4.7 k 12 k 3.38 k
g m Rd (4.2 mS)(3.38 k)
Av 2.73
1 g m Rs 1 (4.2 mS)(1.0 k)
7. (a) N-channel D-MOSFET with zero-bias.
VGS 0 V.
(b) P-channel JFET with self-bias.
VGS I D RS (3 mA)(330 ) 0.99 V
(c) N-channel E-MOSFET with voltage-divider bias.
R2 4.7 k
VGS VDD 12 V = 3.84 V
R1 R2 14.7 k
Chapter 9
8. (a) VG 0 V, VS 0 V
VD VDD I D RD 15 V (8 mA)(1.0 k) 7 V
(b) VG 0 V
VS I D RD (3 mA)(330 ) 0.99 V
VD VDD I D RD 10 V (3 mA)(1.5 k) 5.5 V
R2 4.7 k
(c) VG VDD 12 V = 3.84 V
R1 R2 14.7 k
VS 0 V
VD VDD I D RD 12 V (6 mA)(1.0 k) 6 V
9. (a) n-channel D-MOSFET
(b) n-channel JFET
(c) p-channel E-MOSFET
10. From the curve in Figure 9-16(a) in the textbook:
I d ( pp ) 3.9 mA 1.3 mA = 2.6 mA
11. From the curve in Figure 9-16(b) in the textbook:
I d ( pp ) 6 mA 2 mA = 4 mA
From the curve in Figure 9-16(c) in the textbook:
I d ( pp ) 4.5 mA 1.3 mA = 3.2 mA
12. VD VDD I D RD 12 V (2.83 mA)(1.5 k) 7.76 V
VS I D RS (2.83 mA)(1.0 k) 2.83 V
VDS VD VS 7.76 V 2.83 V 4.93 V
VGS VG VS 0 V 2.83 V 2.83 V
13. Av g m Rd g m RD RL 5000 S 1.5 k 10 k 6.52
V pp ( out ) (2.828)(50 mV)(6.52) 920 mV
14. Av g m Rd
Rd 1.5 k 1.5 k 750
Av (5000 S)(750 ) 3.75
Aout AvVin (3.75)(50 mV) 188 mV rms
Chapter 9
15. (a) Av g m Rd g m RD RL 3.8 mS 1.2 k 22 k 3.8 mS(1138 ) 4.32
(b) Av g m Rd g m RD RL 5.5 mS 2.2 k 10 k 5.5 mS(1.8 ) 9.92
16. See Figure 9-1.
Figure 9-1
I DSS 15 mA
17. ID 7.5 mA
2 2
18. VGS (7.5 mA)(220 ) 1.65 V
2 I DSS 2(15 mA)
gm0 7.5 mS
VGS(off) 4V
g m (7.5 mS)(1 1.65 V/4 V) 4.41 mS
g m Rd (4.41 mS) (820 3.3 k) (4.41 mS) (657 )
Av 1.47
1 g m RS 1 (4.41 mS)(220 ) 1 0.97
19. Av g m Rd (4.41 mS) (820 3.3 k 4.7 k ) (4.41 mS)(576 ) 2.54
I DSS 9 mA
20. ID 4.5 mA
2 2
VGS I D RS (4.5 mA)(330 ) 1.49 V
VDS VDD I D ( RD RS ) 9 V (4.5 mA)(1.33 k) 3 V
21. Av g m Rd g m RD RL 3700 S 1.0 k 10 k 3700 S(909 ) 3.36
Vout AvVin (3.36)(10 mV) 33.6 mV rms
Chapter 9
R2 6.8 k
22. VGS VDD 20 V 5.48 V
R1 R2 24.8 k
I D(on) 18 mA
K 2
0.32 mA / V 2
(VGS VGS(th) ) (10 V 2.5 V) 2
I D K (VGS VGS(th) ) 2 0.32 mA/V 2 (5.48 V 2.5 V) 2 2.84 mA
VDS VDD I D RD 20 V (2.84 mA)(1.0 k) 17.2 V
VGS 15 V
23. RIN 600 MΩ
I GSS 25 nA
Rin 10 M 600 M 9.84 MΩ
24. AV g m Rd 48 mS (1.0 k 10 M) 4.8
Vout AvVin 4.8(10 mV) 48 mV rms
I D I DSS 15 mA
VD 24 V (15 mA)(1.0 k) 9 V
See Figure 9-2.
Figure 9-2
R2 47 k
25. VGS VDD 18 V 9 V
R1 R2 94 k
I D(on) 8 mA
K 2
2
0.125 mA/V 2
(VGS VGS(th) ) (12 V 4 V)
I D(on) K (VGS VGS(th ) ) 2 0.125 mA/V 2 (9 V 4 V) 2 3.13 mA
VDS VDD I D RD 18 V (3.125 mA)(1.5 k) 13.3 V
Av g m RD 4500 S (1.5 k) 6.75
Vds AvVin 6.75(100 mV) 675 mV rms
Chapter 9
Section 9-2 The Common-Drain Amplifier
26. Rs 1.2 k 1 k 545
g m Rs (5500 S)(545 )
Av 0.750
1 g m Rs 1 (5500 S)(545 )
VGS 15 V
RIN 3 1011
I GSS 50 pA
Rin 10 M 3 1011 10 MΩ
27. Rs 1.2 k 1 k 545
gm R (3000 S)(545 )
Av 0.620
1 g m Rs 1 (300 S)(545 )
VGS 15 V
RIN 3 1011
I GSS 50 pA
Rin 10 M 3 1011 10 MΩ
28. (a) Rs 4.7 k 47 k 4.27 k
g m Rs (3000 S)(4.27 k)
Av 0.928
1 g m Rs 1 (3000 S)(4.27 k)
(b) Rs 1.0 k 100 90.9
g m Rs (4300 S)(90.9 )
Av 0.281
1 g m Rs 1 (4300 S)(90.9 )
29. (a) Rs 4.7 k 10 k 3.2 k
g m Rs (3000 S)(3.2 k)
Av 0.906
1 g m Rs 1 (3000 S)(3.2 k)
(b) Rs 100 10 k 99
g m Rs (4300 S)(99 )
Av 0.299
1 g m Rs 1 (4300 S)(99 )
30. The gain will increase for high-resistance sources due to decreased loading.
31. Rin RIN(gate) ( R3 R1 R2 )
Chapter 9
Section 9-3 The Common-Gate Amplifier
32. Av g m Rd 4000 S(1.5 k) 6.0
1 1
33. Rin ( source) 250 Ω
g m 4000 S
34. Av g m Rd 3500 S(10 k) 35
1 1
Rin RS 2.2 k 253 Ω
gm 3500 S
35. X L 2 fL 2 (100 MHz)(1.5 mH) 943 k
Av g m (CG) X L (2800 S)(943 k) 2640
V 15 V
Rin R3 GS 15 M
I GSS 2 nA
15 M 500 M 14.6 MΩ
Section 9-4 The Class D Amplifier
2(9 V) 18 V
36. Av 3600
5 mV 5 mV
37. Pout (12 V)(0.35 A) 4.2 W
Pint (0.25 V)(0.35 A) 140 mW
87.5 mW 140 mW 227.5 mW
Pout 4.2 W
0.95
Pout Pint 4.2 W 227.5 mW
Section 9-5 MOSFET Analog Switching
38. VG V p ( out ) VGS(Th)
V p ( out ) VG VGS(Th) 8 V 4 V 4 V
V pp (in ) 2 V p ( out ) 2 4 V = 8 V
39. f min 2 15 kHz 30 kHz
1
40. R
fC
1 1
f 10 MHz
RC (10 k)(10 pF)
Chapter 9
1 1
41. R 40 k
fC (25 kHz )(0.001 F)
Section 9-6 MOSFET Digital Switching
42. Vout 5 V when Vin 0
Vout 0 V when Vin 5 V
43. (a) Vout 3.3 V (b) Vout 3.3 V
(c) Vout 3.3 V (d) Vout 0 V
44. (a) Vout 3.3 V (b) Vout 0 V
(c) Vout 0 V (d) Vout 0 V
45. The MOSFET has lower on-state resistance and can turn off faster.
Section 9-7 Troubleshooting
46. (a) VD1 VDD ; No signal at Q1 drain; No output signal
(b) VD1 0 V (floating); No signal at Q1 drain; No output signal
(c) VGS1 0 V; VS 0 V; VD1 less than normal; Clipped output signal
(d) Correct signal at Q1 drain; No signal at Q2 gate; No output signal
(e) VD2 VDD ; Correct signal at Q2 gate; No Q2 drain signal or output signal
47. (a) Vout 0 V if C1 is open.
(b) Av1 g m Rd 5000 S(1.5 k) 7.5
g m Rd 7.5
Av 2 2.24
1 g m Rs 1 (5000 S )(470 )
Av Av1 Av 2 (7.5)(2.24) 16.8
Vout AvVin (16.8)(10 mV) 168 mV
(c) VGS for Q2 is 0 V, so I D I DSS . The output is clipped.
(d) No Vout because there is no signal at the Q2 gate.
Chapter 9
Datasheet Problems
48. The 2N3796 FET is an n-channel D-MOSFET.
49. (a) For a 2N3796, the typical VGS(off ) 3.0 V
(b) For a 2N3797, VDS(max) 20 V
(c) At TA 25C, PD(max) 200 mW
(d) For a 2N3797, VGS(max) ±10 V
50. PD 200 mW (1.14 mW/ C)(55C 25C) 166 mW
51. For a 2N3796 with f 1 kHz, g m 0 900 μS minimum
52. At VGS 3.5 V and VDS 10 V,
I D(min) 9.0 mA, I D(typ) 14 mA, I D(max) 18 mA
53. For a zero-biased 2N3796, I D(typ) 1.5 mA
54. Av (max) (1800 S)(2.2 k) 3.96
Advanced Problems
55. Rd (min) 1.0 k 4 k 800
Av (min) (2.5 mS)(800 ) 2.0
Rd (max) 1.0 k 10 k 909
Av (min) (7.5 mS)(909 ) 6.82
56. I DSS(typ) 2.9 mA
12 V
RD RS 4.14 k
2.9 mA
1 1
435
g m 2300 S
If RS 0 , then RD 4 k (3.9 k standard)
Av (2300 S)(3.9 k) 8.97
VDS 24 V (2.9 mA)(3.9 k) 24 V 11.3 V 12.7 V
The circuit is a common-source zero-biased amplifier with a drain resistor of 3.9 k
Chapter 9
57. To maintain VDS 12 V for the range of I DSS values:
For I DSS(min) 2 mA
12 V
RD 6 k
2 mA
For I DSS(max) 6 mA
12 V
RD 2 k
6 mA
To maintain Av 9 for the range of g m ( y fs ) values:
For g m(min) 1500 S
9
RD 6 k
1500 S
For g m(max) 3000 S
9
RD 3 k
3000 S
A drain resistance consisting of a 2.2 k fixed resistor in series with a 5 k variable
resistor will provide more than sufficient range to maintain a gain of 9 over the specified
range of g m values. The dc voltage at the drain will vary with adjustment and depends on
I DSS . The circuit cannot be modified to maintain both VDS 12 V and Av 9 over the
full range of transistor parameter values. See Figure 9-3.
Figure 9-3
Chapter 9
Multisim Troubleshooting Problems
58. Drain-source shorted
59. C2 open
60. C1 open
61. Rs shorted
62. Drain-source open
63. R1 open
64. RD open
65. R2 open
66. C2 open
Chapter 10
Amplifier Frequency Response
Section 10-1 Basic Concepts
1. (a) Parasitic capacitance affects the high-frequency response.
(b) A designer can choose a transistor with a lower internal capacitance, lower the gain
to reduce the Miller effect, or change the circuit to use a noninverting amplifier.
2. At sufficiently high frequencies, the reactances of the coupling capacitors become very
small, and the capacitors appear effectively as shorts; thus, negligible signal voltage is
dropped across them.
3. BJT: Cbe, Cbc, and Cce
FET: Cgs, Cgd, and Cds
4. Low-frequency response: C1, C2, and C3
High-frequency response: Cbc, Cbe, and Cce
R2 4.7 k
5. VE VCC 0.7 V 20 V 0.7 V 1.79 V
R1 R2 37.7 k
VE 1.79 V
IE 3.2 mA
RE 560
25 mV
re 7.8
3.2 mA
Rc 2.2 k 5.6 k
Av 202
re 7.8
Cin ( miller ) Cbc ( Av 1) 4 pE(202 1) 812 pF
A 1 203
6. Cout ( miller ) Cbc v 4 pF 4 pF
A
v 202
7. ID = 3.36 mA using Eq. 9–2 and a programmable calculator.
VGS (3.36 mA)(1.0 k) 3.36 V
2(10 mA)
g m0 2.5 mS
8V
3.36 V
g m (2.5 mS) 1 1.45 mS
8V
Chapter 10
Av g m Rd (1.45 mS)(1.0 k 10 k) 1.32
C gd Crss 3 pF
Cin ( miller ) Cgd ( Av 1) 3 pE(2.32) 6.95 pF
A 1 2.32
Cout ( miller ) C gd v 3 pF 5.28 pF
Av 1.32
Section 10-2 The Decibel
Pout 5W
8. Ap 10
Pin 0.5 W
P
Ap (dB) 10 log out 10 log10 10 dB
Pin
Vout 1.2 V
9. Vin 24 mV rms
Av 50
Av (dB) 20 log Av 20 log 50 34.0 dB
25
10. The gain reduction is 20 log 8.3 dB
65
2 mW
11. (a) 10 log 3.01 dBm
1 mW
1 mW
(b) 10 log 0 dBm
1 mW
4 mW
(c) 10 log 6.02 dBm
1 mW
0.25 mW
(d) 10 log 6.02 dBm
1 mW
4.7 k
12. VB 20 V 1.79 V
37.7 k
1.79 V
IE 3.20 mA
560
25 mV
re 7.81
3.2 mA
5.6 k 2.2 k
Av 202
7.81
Chapter 10
Av (dB) 20 log (202) 46.1 dB
At the critical frequencies,
Av (dB) 46.1 dB 3 dB 43.1 dB
Section 10-3 Low-Frequency Amplifier Response
1 1
13. (a) fc 318 Hz
2 RC 2 (100 )(5 F)
1 1
(b) fc 1.59 kHz
2 RC 2 (1.0 k)(0.1 F)
14. RIN(BASE) DC RE 12.5 k
R2 RIN(BASE) 4.7 k 12.5 k
VE 9 V 0.7 V 9 V 0.7 V 1.3 V
R1 R2 RIN(BASE) 12 k 4.7 k 12.5 k
VE 1.3 V
IE 13 mA
RE 100
25 mV
re 1.92
13 mA
Rin (base) ac re (125)(1.92 ) 240
Rin 50 Rin (base ) R1 R2 50 240 12 k 4.7 k 274
For the input circuit:
1 1
fc 581 Hz
2 Rin C1 2 (274 )(1 F)
For the output circuit:
1 1
fc 177 Hz
2 ( RC RL )C3 2 (900 )(1 F)
For the bypass circuit:
RTH R1 R2 Rs 12 k 4.7 k 50 49.3
1 1
fc 6.89 kHz
2 re RRH / DC RE C2 2 (2.31 )(10 F)
RC RL 220 680
Av 86.6
re 1.92
Av(dB) = 20 log(86.6) = 38.8 dB
Chapter 10
The bypass circuit produces the dominant low critical frequency. See Figure 10-1.
Figure 10-1
15. From Problem 14:
Av(mid) = 86.6
Av(mid) (dB) = 38.8 dB
For the input RC circuit: fc = 578 Hz
For the output RC circuit: fc = 177 Hz
For the bypass RC circuit: fc = 6.89 kHz
The fc of the bypass circuit is the dominant low critical frequency.
At f = fc = 6.89 kHz:
Av = Av(mid) – 3 dB = 38.8 dB – 3 dB = 35.8 dB
At f = 0.1fc:
Av = 38.8 dB – 20 dB = 18.8 dB
At 10fc (neglecting any high-frequency effects):
Av = Av(mid) = 38.8 dB
16. At f f c X C R
XC
tan 1 1
tan (1) 45
R
At f = 0.1 fc, XC = 10R.
tan 1 (10) 84.3
At f = 10 fc, XC = 0.1R.
tan 1 (0.1) 5.7
Chapter 10
VGS 10 V
17. Rin ( gate ) 200 M
I GSS 50 nA
Rin RG Rin ( gate) 10 M 200 M 9.52 M
For the input circuit:
1 1
fc 3.34 Hz
2 Rin C1 2 (9.52 M)(0.005 F)
For the output circuit:
1 1
fc 3.01 kHz
2 ( RD RL )C2 2 (560 10 k)(0.005 F)
The output circuit is dominant. See Figure 10-2. (Av is determined in Problem 18.)
Figure 10-2
2(15 mA)
18. gm gm0 5 mS
6V
Av ( mid ) g m RD RL 5 mS(560 10 k) 2.65
Av ( mid ) (dB) 8.47 dB
At fc:
Av 8.47 dB 3 dB 5.47 dB
At 0.1fc:
Av 8.47 dB 20 dB 11.5 dB
At 10fc:
Av Av ( mid ) 8.47 dB (if 10fc is still in midrange)
Chapter 10
Section 10-4 High-Frequency Amplifier Response
19. From Problems 14 and 15:
re 1.92 and Av ( mid ) 86.6
Input circuit:
Cin ( miller ) Cbc ( Av 1) 10 pF(87.6) 876 pF
Ctot Cbe Cin ( miller ) 25 pF 876 pF 901 pF
1 1
fc 4.32 MHz
2 Rs R1 R2 ac re Ctot 2 50 12 k 4.7 k 240 901 pF
Output circuit:
A 1 87.6
Cout ( miller ) Cbc v 10 pF 10.1 pF
Av 86.6
1 1
fc 94.9 MHz
2 Rc Cout ( miller ) 2 (166 )(10.1 pF)
Therefore, the dominant high critical frequency is determined by the input circuit:
f c 4.32 MHz . See Figure 10-3.
Figure 10-3
20. At f 0.1 fc 458 kHz:
Av Av ( mid ) 38.8 dB
At f f c 4.58 MHz:
Av Av ( mid ) 3 dB 38.8 dB 3 dB 35.8 dB
At f 10 fc 45.8 MHz:
Chapter 10
Av Av ( mid ) 20 dB 38.8 dB 20 dB 18.8 dB
At f 100 f c 458 MHz:
The roll-off rate changes to –40 dB/decade at f = 94.6 MHz. So, for frequencies from
45.8 MHz to 94.6 MHz, the roll-off rate is –20 dB/decade and above 94.6 MHz it is
–40 dB/decade.
The change in frequency from 45.8 MHz to 94.6 MHz represents
94.6 MHz 45.8 MHz
100% 11.8%
458 MHz 45.8 MHz
So, for 11.8% of the decade from 45.8 MHz to 458 MHz, the roll-off rate is –20 dB/decade,
and for the remaining 88.2% of the decade, the roll-off rate is –40 dB/decade.
Av 18.8 dB (0.118)(20 dB) (0.882)(40 dB) 18.8 dB 2.36 dB 35.3 dB 18.9 dB
21. C gd Crss 4 pF
C gs Ciss Crss 10 pF 4 pF 6 pF
Input circuit:
Cin ( miller ) Cgd ( Av 1) 4 pF(2.65 1) 14.6 pF
Ctot Cgs Cin ( miller ) 6 pF +14.6 pF 20.6 pF
1 1
fc 12.9 MHz
2 Rs Ctot 2 (600 )(20.6 pF)
Output circuit:
A 1 2.65 1
Cout ( miller ) C gd v 4 pF 5.51 pF
Av 2.65
1 1
fc 54.5 MHz
2 Rd Cout ( miller ) 2 (530 )(5.51 pF)
The input circuit is dominant.
22. From Problem 21: For the input circuit, f c 12.9 MHz
and for the output circuit, f c 54.5 MHz.
The dominant critical frequency is 12.9 MHz.
At f 0.1 f c 1.29 MHz: Av Av ( mid ) 8.47 dB, 0
At f f c 1.29 MHz: Av Av ( mid ) 3 dB 8.47 dB 3 dB 5.47 dB, tan 1 (1) 45
At f 10 fc 129 MHz:
From 12.9 MHz to 54.5 MHz the roll-off is –20 dB/decade. From 54.5 MHz to 129 MHz
the roll-off is –40 dB/decade.
The change in frequency from 12.9 MHz to 54.5 MHz represents
Chapter 10
54.5 MHz 12.9 MHz
100% 35.8%
129 MHz 12.9 MHz
So, for 35.8% of the decade, the roll-off rate is –20 dB/decade, and for 64.2% of the
decade, the rate is –40 dB/decade.
Av 5.47 dB (0.358)(20 dB) (0.642)(40 dB) 27.4 dB
At f 100 fc 1290 MHz: Av 27.4 dB 40 dB 67.4 dB
Section 10-5 Total Amplifier Frequency Response
23. f cl 136 Hz
f cu 8 kHz
24. From Problems 14 and 19:
f cu 4.32 MHz and f cl 6.89 kHz
BW f cu f cl 4.32 MHz 6.89 kHz 4.313 MHz
25. ftot ( BW ) Av ( mid )
ftot 200 MHz
BW 5.26 MHz
Av ( mid ) 38
Therefore, f cu BW 5.26 MHz
26. 6 dB/octave roll-off:
At 2 f cu : Av = 50 dB 6 dB = 44 dB
At 4 f cu : Av = 50 dB 12 dB = 38 dB
20 dB/decade roll-off:
At 10 fcu : Av = 50 dB 20 dB = 30 dB
Section 10-6 Frequency Response of Multistage Amplifiers
27. Dominant f cl 230 Hz
Dominant fcu 1.2 MHz
28. BW 1.2 MHz 230 Hz 1.2 MHz
Chapter 10
400 Hz 400 Hz
29. f cl 622 Hz
21/2 1 0.643
fcu (800 kHz) 21/2 1 0.643(800 kHz) 515 kHz
BW 515 kHz 622 Hz 514 kHz
50 Hz 50 Hz
30. f cl 98.1 Hz
21/3 1 0.510
125 Hz 125 Hz
31. f cl 194 Hz
21/2 1 0.643
fcu 2.5 MHz
BW 2.5 MHz 194 Hz 2.5 MHz
Section 10-7 Frequency Response Measurements
0.35 0.35
32. f cl 350 Hz
tf 1 ms
0.35 0.35
f cu 17.5 MHz
tr 20 ns
33. Increase the frequency until the output voltage drops to 3.54 V (3 dB below the midrange
output voltage). This is the upper critical frequency.
34. tr 3 div 5 s/div 15 s
t f 6 div 0.1 ms/div 600 s
0.35 0.35
f cl 583 Hz
tf 600 s
0.35 0.35
f cu 23.3 kHz
tr 15 s
BW 23.3 kHz 583 Hz 22.7 kHz
Chapter 10
Device Application Problems
35. Q1 stage:
1 1
f cl (input ) 2.55 Hz
2 ( R1 R2 ac R4 )C1 2 (62.3 k)1 F
1 1
f cl (bypass ) 15.9 Hz
2 R4C2 2 (1 k)10 F
1 1
f cl ( output ) 4.30 Hz
2 ( R5 R6 R7 ac ( R9 R10 )C3 2 (37 k)1 F
Q2 stage:
1 1
f cl (input ) 17.9 Hz
2 ( R5 R6 R7 ac ( R9 R10 )C3 2 (8.9 k) 1 F
1 1
f cl (bypass ) 0.006 Hz
R6 R7 2 (208 )100 F
2 R9 C
ac 4
1 1
f cl ( output ) 4.45 Hz
2 R8 RL C5 2 (35.8 k)1 F
The dominant critical frequency of 15.9 Hz is set by the Q1 bypass circuit.
36. Changing to 1 μF coupling capacitors does not significantly affect the overall bandwidth
because the upper critical frequency is much greater than the dominant lower critical
frequency.
37. Increasing the load resistance on the output of the second stage has no effect on the
dominant lower critical frequency because the critical frequency of the output circuit will
decrease and the critical frequency of the first stage input circuit will remain dominant.
38. The Q1 stage bypass circuit set the dominant critical frequency.
1 1
f cl (bypass ) 15.9 Hz
2 R4C2 2 (1 k)10 F
This frequency is not dependent on ac and is not affected.
Datasheet Problems
39. Cin (tot ) (25 1)4 pF 8 pF 112 pF
fT 300 MHz
40. BWmin 6 MHz
Av ( mid ) 50
Chapter 10
41. C gd Crss 1.3 pF
C gs Ciss Crss 5 pF 1.3 pF 3.7 pF
Cds Cd Crss 5 pF 1.3 pF 3.7 pF
Advanced Problems
42. From Problem 12: re 7.81 and I E 3.2 mA
VC 20 V (3.2 mA)(2.2 k) 13 V dc
The maximum peak output signal can be approximately 6 V.
The maximum allowable gain for the two stages is
6V
Av (max) 424
1.414(10 mV)
For stage 1:
Rc 2.2 k 33 k 4.7 k (150)(7.81 ) 645
645
Av1 82.6
7.81
For stage 2:
Rc 2.2 k 5.6 k 1.58 k
1.58 k
Av1 202
7.81
Av (tot ) (82.6)(202) 16,685
The amplifier will not operate linearly with a 10 mV rms input signal.
The gains of both stages can be reduced or the gain of the second stage only can be
reduced.
One approach is leave the gain of the first stage as is and bypass a portion of the emitter
resistance in the second stage to achieve a gain of 424/82.6 = 5.13.
Rc
Av 5.13
Re re
Rc 5.13re 1.58 k 40.1
Re 300
5.13 5.13
Modification: Replace the 560 Ω emitter resistor in the second stage with an unbypassed
300 Ω resistor and a bypassed 260 Ω resistor (closest standard value is 270 Ω).
Chapter 10
43. From Problems 17, 18, and 21:
Ctot C gs Cin ( miller ) 20.6 pF
2.65 1
Cout ( miller ) 4 pF 5.51 pF
2.65
Stage 1:
1 1
f cl (in ) 3.34 Hz
2 Rin C1 2 (9.52 M)(0.005 F)
1
f cl ( out ) 3.34 Hz since Rin (2) 560
2 (9.52 M)(0.005 F)
1
f cu (in ) 12.9 MHz
2 (600 )(20.6 pF)
1
f cu ( out ) 10.9 MHz
2 (560 )(20.6 pF 5.51 pF)
Stage 2:
1 1
f cl (in ) 3.34 Hz
2 Rin C1 2 (9.52 M)(0.005 F)
1
f cl ( out ) 3.01 kHz
2 (10.6 k)(0.005 F)
1
f cu (in ) 10.9 MHz
2 (560 )(20.6 pF 5.51 pF)
1
f cu ( out ) 54.5 MHz
2 (560 10 k )(5.51 pF)
Overall:
f cl (in ) 3.34 kHz and f cu (in ) 10.9 MHz
BW 10.9 MHz
44. Rin (1) 22 k (100)(320 ) 13 k
13 k
VB(1) 12 V 1.38, VE(1) 0.681 V
113 k
0.681 V
I E(1) 2.13 mA, re 11.7
320
Rc (1) 4.7 k 33 k 22 k (100)(100 ) 2.57 k
Chapter 10
2.57 k
Av (1) 23
112
Rin (2) 22 k (100)(1010 ) 18 k
18 k
VB(2) 12 V 4.24, VE(1) 3.54 V
51 k
3.54 V
I E(2) 3.51 mA, re 7.13
1.01 k
Rc (2) 3 k 10 k 2.31 k
2.31 k
Av (2) 24 maximum
107.13
2.31 k
Av (2) 2.27 minimum
101 k 7.13
Av (tot ) (23)(24) 552 maximum
Av (tot ) (23)(2.27) 52.3 minimum
This is a bit high, so adjust Rc (1) to 3 kΩ, then
3 k 22 k 33 k 101 k
Av (1) 21.4
112
Now,
Av (tot ) (21.3)(24) 513 maximum
Av (tot ) (21.3)(2.27) 48.5 minimum
Thus, Av is within 3% of the desired specifications.
Frequency response for stage 1:
Rin 22 k 100 k 32 k 11.5 k
1
f cl (in ) 1.38 Hz
2 (11.5 k)(10 F)
Remitter 220 (100 11.7 (22 k 100 k / 100 125
1
f cl (bypass ) 12.7 Hz
2 (125 )(100 F)
Rout 3 k (33 k 22 k (100)(107 )) 8.91 k
1
f cl ( out ) 1.79 Hz
2 (8.91 k)(10 F)
Chapter 10
Frequency response for stage 2:
f cl (in ) 1.79 Hz (same as f cl ( out ) for stage 1)
Rout 3 k 10 k 13 k
1
f cl ( out ) 1.22 Hz
2 (13 k)(10 F)
This means that CE(2) is the frequency limiting capacitance.
Remitter 910 (100 7 (22 k 33 k 3 k)/100) 115
For f cl 1 kHz:
1
CE(2) 1.38 F
2 (115 )(1 kHz)
1.5 μF is the closest standard value and gives
1
f cl (bypass ) 922 Hz
2 (115 )(1.5 F)
This value can be moved closer to 1 kHz by using additional parallel bypass capacitors in
stage 2 to fine-tune the response.
Multisim Troubleshooting Problems
The solutions showing instrument connections for Problems 45 through 48 are available from the
Instructor Resource Center. See Chapter 2 for instructions. The faults in the circuit files may be
accessed using the password book (all lowercase).
45. RC open
46. Output capacitor open
47. R2 open
48. Drain-source shorted
Chapter 11
Thyristors
Section 11-1 The Four-Layer Diode
1. VA VBE VCE(sat) 0.7 V 0.2 V 0.9 V
VR S VBIAS VA 25 V 0.9 V 24.1 V
VR S 24.1 V
IA 24.1 mA
RS 1.0 k
VAK 15 V
2. (a) RAK 15 M
IA 1 A
(b) From 15 V to 50 V for an increase of 35 V.
Section 11-2 The Silicon-Controlled Rectifier (SCR)
3. See Section 11-2 in the textbook.
4. Neglecting the SCR voltage drop,
30 V 0.7 V
Rmax 2.93 k
10 mA
5. When the switch is closed, the battery V2 causes illumination of the lamp. The light
energy causes the LASCR to conduct and thus energize the relay. When the relay is
energized, the contacts close and 115 V ac are applied to the motor.
6. See Figure 11-1.
Figure 11-1
Chapter 11
Section 11-3 SCR Applications
7. Add a transistor to provide inversion of the negative half-cycle in order to obtain a
positive gate trigger.
8. D1 and D2 are full-wave rectifier diodes.
9. See Figure 11-2.
Figure 11-2
Section 11-4 The Diac and Triac
10. Vin ( p ) 1.414Vin ( rms ) 1.414(25 V) 35.4 V
35.35 V
I p Vin ( p ) 35.4 mA
1.0 k
20 V
Current at breakover 20 mA
1.0 k
See Figure 11-3.
Figure 11-3
Chapter 11
15 V
11. Ip 3.19 mA
4.7 k
See Figure 11-4.
Figure 11-4
Section 11-5 The Silicon-Controlled Switch (SCS)
12. See Section 11-5 in the text.
13. Anode, cathode, anode gate, and cathode gate
Section 11-6 The (UJT)
rB1 2.5k
14. 0.385
rB1 rB 2 2.5k 4 k
15. V p VBB V pn 0.385(15 V) 0.7 V 6.48 V
VBB Vv V VP
16. R1 BB
Iv Ip
12 V 0.8 V 12 V 10 V
R1
15 mA 10 A
747 R1 200 k
Section 11-7 The Programmable Unijunction Transistor (PUT)
R3 10 k
17. (a) VA VB 0.7 V 20 V 0.7 V 9.79 V
R2 R3 22 k
R3 47 k
(b) VA VB 0.7 V 9 V 0.7 V 5.2 V
R2 R3 94 k
Chapter 11
18. (a) From Problem 17(a), VA 9.79 V at turn on.
9.79 V
I 20.8 mA at turn on
470
10 V
Ip 21.3 mA
470
See Figure 11-5.
Figure 11-5
(b) From Problem 17(b), VA 5.2 V at turn on.
5.2 V
I 15.8 mA at turn on
330
10 V
Ip 30.3 mA
330
See Figure 11-6.
Figure 11-6
Chapter 11
R3 10 k
19. VA 6 V 0.7 V 6 V 0.7 V 3.7 V at turn on
R2 R3 20 k
VR1 VA 3.7 V at turn on.
See Figure 11-7.
Figure 11-7
15 k
20. VA 6 V 0.7 V
25 k
= 4.3 V at turn on
VR1 VA 4.3 V
See Figure 11-8.
Figure 11-8
Chapter 11
Device Application Problems
21. The motor runs fastest at 0 V for the motor speed control circuit.
22. If the rheostat resistance decreases, the SCR turns on earlier in the ac cycle.
23. As the PUT gate voltage increases in the circuit, the PUT triggers on later in the ac cycle
causing the SCR to fire later in the cycle, conduct for a shorter time, and decrease the
power to the motor.
Advanced Problems
24. D1: 15 V zener (1N4744)
R1: 100 Ω, 1 W
R2: 100 Ω, 1 W
Q1: Any SCR with a 1 A minimum rating (1.5 A would be better)
R3: 150 Ω, 1 W
25. See Figure 11-9.
Figure 11-9
26. V p VBB V pn (0.75)(12 V) 0.7 V 9.7 V
I v 10 mA and I p 20 A
12 V 9.7 V
R1 115 k
20 A
12 V 1 V
R1 1.1 k
10 mA
Select R1 51 k as an intermediate value.
Chapter 11
During the charging cycle:
V (t ) VF (VF V0 )e t1 R1C
9.7 V 12 V (12 V 1 V)et1 R1C
t1 2.3 V
ln
R1C 11 V
2.3 V 3
t1 R1C ln 1.56 R1C 79.8 10 C
11 V
During the discharging cycle (assuming R2 RB1 ):
V (t ) VF (VF V0 )et2 R2C
1 V 0 V (0 V 9.3 V)e t2 R2C
t2 1V
ln
R2C 9.3 V
1V
t2 R2C ln 2.23R2C
9.3 V
Let R2 100 k, so t2 223 103 C .
Since f 2.5 kHz, T 400 s
T t1 t2 79.8 103 C 223 103 C 303 103 C 400 s
400 s
C 0.0013 F
303 103
See Figure 11-10.
Figure 11-10
Multisim Troubleshooting Problems
27. Cathode-anode shorted
28. Gate-cathode open
29. R1 shorted
Chapter 12
The Operational Amplifier
Section 12-1 Introduction to Operational Amplifiers
1. Practical op-amp: High open-loop gain, high input impedance. low output impedance,
and high CMRR.
Ideal op-amp: Infinite open-loop gain, infinite input impedance, zero output impedance,
and infinite CMRR.
2. Op amp 2 is more desirable because it has a higher input impedance, a lower output
impedance, and a higher open-loop gain.
Section 12-2 Op-Amp Input Modes and Parameters
3. (a) Single-ended differential input
(b) Double-ended differential input
(c) Common-mode
4. CMRR (dB) = 20 log(250,000) = 108 dB
A 175,000
5. CMRR (dB) 20 log ol 20 log 120 dB
Acm 0.18
Aol
6. CMRR
Acm
Aol 90,000
Acm 0.3
CMRR 300,000
8.3 A 7.9 A
7. I BIAS 8.1 A
2
8. Input bias current is the average of the two input currents. Input offset current is the
difference between the two input currents.
I OS 8.3 A 7.9 A 400 nA
24 V
9. Slew rate 1.6 V / s
15 s
Chapter 12
Vout 20 V
10. t 40 s
slew rate 0.5 V/ s
Section 12-4 Op-Amps with Negative Feedback
11. (a) Voltage-follower
(b) Noninverting
(c) Inverting
Ri 1.0 k
12. B 9.90 103
Ri R f 101 k
V f BVout (9.90 103 )5 V 0.0495 V 49.5 mV
1 1
13. (a) Acl (NI) 374
B 1.5 k / 561.5 k
(b) Vout Acl (NI)Vin (374)(10 mV) 3.74 V rms
1.5 k
(c) Vf 3.74 V 9.99 mV rms
561.5 k
1 1
14. (a) Acl (NI) 11
B 4.7 k / 51.7 k
1 1
(b) Acl (NI) 101
B 10 k / 1.01 M
1 1
(c) Acl (NI) 47.8
B 4.7 k / 224.7 k
1 1
(d) Acl (NI) 23
B 1.0 k / 23 k
Rf
15. (a) 1 Acl (NI)
Ri
R f Ri ( Acl (NI) 1) 1.0 k (50 1) 49 k
Rf
(b) Acl (I)
Ri
R f Ri ( Acl (I) ) 10 k(300) 3 M
(c) R f Ri ( Acl (NI) 1) 12 k(7) 84 k
(d) R f Ri ( Acl (I) ) 2.2 k(75) 165 k
Chapter 12
16. (a) Acl (VF) 1
Rf 100 k
(b) Acl (I) = = 1
Ri 100 k
1 1
(c) Acl (NI) = 22
Ri 47 k
Ri R f 47 k 1.0 M
Rf 330 k
(d) Acl (I) = 10
Ri 33 k
17. (a) Vout Vin 10 mV, in phase
Rf
(b) Vout AclVin Vin = (1)(10 mV) 10 mV, 180 out of phase
Ri
1 1 10 mV 223 mV, in phase
(c) Vout Vin V
R1
Ri R f in
47 k
1047 k
Rf 330 k
(d) Vout Vin 10 mV 100 mV, 180 out of phase
Ri 33 k
Vin 1V
18. (a) I in 455 A
Rin 2.2 k
(b) I f I in 455 A
(c) Vout I f R f (455 A)(22 k) 10 V
Rf 22 k
(d) Acl (I) 10
Ri 2.2 k
Section 12-5 Effects of Negative Feedback on Op-Amp Impedances
2.7 k
19. (a) B 0.0048
562.5 k
Zin (NI) (1 Aol ) Zin [1 (175,000)(0.0048)]10 M 8.41 G
Z out 75
Z out (NI) 89.2 m
1 Aol B 1 (175,000)(0.0048)
Chapter 12
1.5 k
(b) B 0.031
48.5 k
Zin (NI) (1 Aol B) Zin [1 (200,000)(0.031)]1 M 6.20 G
Z out 25
Z out (NI) 4.04 m
1 Aol B 1 (200,000)(0.031)
56 k
(c) B 0.053
1.056 M
Zin (NI) (1 Aol B) Zin [1 (50,000)(0.053)]2 M 5.30 G
Z out 50
Z out (NI) 19.0 m
1 Aol B 1 (50,000)(0.053)
20. (a) Z in (VF) (1 Aol ) Z in (1 220,000) 6 M 1.32 1012 1.32 T
Z out 100
Z out (VF) 455
1 Aol 1 220,000
(b) Z in (VF) (1 Aol ) Z in (1 100,000)5 M 5 1011 500 G
Z out 60
Z out (VF) 600
1 Aol 1 100,000
(c) Zin (VF) (1 Aol ) Zin (1 50,000)800 k 40 G
Z out 75
Z out (VF) 1.5 m
1 Aol 1 500,000
21. (a) Zin (I) Ri 10 k
Ri 10 k
B 0.0625
Ri R f 160 k
Z out 40
Z out (I) 5.12 m
1 Aol B 1 (125,000)(0.0625)
(b) Zin (I) Ri 100 k
100 k
B 0.091
1.1 M
Z out 50
Z out (I) 7.32 m
1 Aol B 1 (75,000)(0.091)
Chapter 12
(c) Z in (I) Ri 470 k
470
B 0.045
10,470
Z out 70
Z out (I) 6.22 m
1 Aol B 1 (250,000)(0.045)
Section 12-6 Bias Current and Offset Voltage
22. (a) Rcomp Rin 75 Ω placed in the feedback path.
I OS 42 A 40 A 2 A
(b) VOUT(error) Av I OS Rin (1)(2 A)(75 ) 150 V
23. (a) Rc Ri R f 2.7 k 560 k 2.69 k
(b) Rc Ri R f 1.5 k 47 k 1.45 k
(c) Rc Ri R f 56 k 1.0 M 53 k
See Figure 12-1.
Figure 12-1
24. VOUT(error) AvVIO (1)(2 nV) 2 nV
25. VOUT(error) (1 Aol )VIO
VOUT(error) 35 mV
VIO 175 nV
Aol 200,000
Chapter 12
Section 12-7 Open-Loop Frequency and Phase Responses
26. Acl 120 dB 50 dB 70 dB
27. The gain is ideally 175,000 at 200 Hz. The midrange dB gain is
20 log(175,000) = 105 dB
The actual gain at 200 Hz is
Av (dB) 105 dB 3 dB 102 dB
102
Av log 1 125,892
20
BWol 200 Hz
fc X C
28.
f R
Rf c (1.0 k)(5 kHz)
XC 1.67 k
f 3 kHz
Vout 1 1
29. (a) 0.997
Vin 2 2
f 1 kHz
1 1
fc 12 kHz
Vout 1 1
(b) 0.923
Vin f
2
5 kHz
2
1 1
fc 12 kHz
Vout 1 1
(c) 0.707
Vin f
2
12 kHz
2
1 1
fc 12 kHz
Vout 1 1
(d) 0.515
Vin f
2
20 kHz
2
1 1
fc 12 kHz
Vout 1 1
(e) 0.119
Vin f
2
100 kHz
2
1 1
fc 12 kHz
Chapter 12
Aol ( mid ) 80,000
30. (a) Aol 79,603
2 2
f 100 kHz
1 1
f c ( ol ) 1 kHz
Aol ( mid ) 80,000
(b) Aol 56,569
2 2
f 1 kHz
1 1
f c ( ol ) 1 kHz
Aol ( mid ) 80,000
(c) Aol 7960
2 2
f 10 kHz
1 1
f c ( ol ) 1 kHz
Aol ( mid ) 80,000
(d) Aol 80
2 2
f 1 MHz
1 1
f c ( ol ) 1 kHz
1 1 f 2 kHz
31. (a) fc 1.59 kHz; tan 1 tan 1 51.5
2 RC 2 (10 k)(0.01 F) fc 1.59 kHz
1 1 f 2 kHz
(b) fc 15.9 kHz; tan 1 tan 1 7.17
2 RC 2 (1.0 k)(0.01 F) fc 15.9 kHz
1 1 f 2 kHz
(c) fc 159 Hz; tan 1 tan 1 85.5
2 RC 2 (100 k)(0.01 F) fc 159 kHz
f 1 100 Hz
32. (a) tan 1 tan 0.674
fc 8.5 kHz
f 1 400 Hz
(b) tan 1 tan 2.69
fc 8.5 kHz
f 1 850 Hz
(c) tan 1 tan 5.71
fc 8.5 kHz
f 1 8.5 kHz
(d) tan 1 tan 45.0
fc 8.5 kHz
f 1 25 kHz
(e) tan 1 tan 71.2
fc 8.5 kHz
f 1 85 kHz
(f) tan 1 tan 84.3
fc 8.5 kHz
Chapter 12
See Figure 12-2.
Figure 12-2
33. (a) Aol ( mid ) 30 dB 40 dB 20 dB 90 dB
f 1 10 kHz
(b) 1 tan 1 tan 86.6
fc 600 Hz
f 1 10 kHz
2 tan 1 tan 11.3
fc 50 kHz
f 1 10 kHz
3 tan 1 tan 2.86
fc 200 kHz
tot 86.6 11.3 2.86 180 281
34. (a) 0 dB/decade
(b) –20 dB/decade
(c) –40 dB/decade
(d) –60 dB/decade
Section 12-8 Closed-Loop Frequency Response
Rf 68 k
35. (a) Acl (I) 30.9; Acl (I) (dB) 20 log(30.9) 29.8 dB
Ri 2.2 k
1 1
(b) Acl (NI) 15.7; Acl (NI) (dB) 20 log (15.7) 23.9 dB
B 15 k / 235 k
(c) Acl (VF) 1; Acl (VF) (dB) 20 log(1) 0 dB
These are all closed-loop gains.
Chapter 12
36. BWcl BWol (1 BAol ( mid ) ) 1500 Hz[1 (0.015)(180,000)] 4.05 MHz
37. Aol (dB) 89 dB
Aol 28,184
Acl f c ( cl ) Aol f c ( ol )
Aol f c ( ol ) (28,184)(750 Hz)
Acl 3843
f c ( cl ) 5.5 kHz
Acl (dB) 20log(3843) 71.7 dB
Aol f c ( ol ) (28,184)(750 Hz)
38. Acl 3843
f c ( cl ) 5.5 kHz
fT Acl f c (cl ) (3843)(5.5 kHz) 21.1 MHz
39. (a) Acl (VF) 1
fT 28 MHz
BW f c ( cl ) = = 2.8 MHz
Acl 1
100 k
(b) Acl (I) = 45.5
2.2 k
2.8 MHz
BW = 61.6 kHz
45.5
12 k
(c) Acl (NI) 1 = 13
1.0 k
2.8 MHz
BW = 215 kHz
13
1 M
(d) Acl (I) = 179
5.6 k
2.8 MHz
BW = 15.7 kHz
179
150 k
40. (a) Acl = 6.8
22 k
Aol f c ( ol ) (120,000)(150 Hz)
f c ( cl ) 2.65 MHz
Acl 6.8
BW f c ( cl ) = 2.65 MHz
Chapter 12
1.0 M
(b) Acl = 100
10 k
Aol f c ( ol ) (195,000)(50 Hz)
f c ( cl ) 97.5 kHz
Acl 100
BW f c ( cl ) = 97.5 kHz
Section 12-9 Troubleshooting
41. (a) Faulty op-amp or open R1
(b) R2 open, forcing open-loop operation
42. (a) Circuit becomes a voltage-follower and the output replicates the input.
(b) Output will saturate.
(c) No effect on the ac; may add or subtract a small dc voltage to the output.
(d) The voltage gain will change from 10 to 0.1.
43. The gain becomes a fixed –100 with no effect as the potentiometer is adjusted.
Device Application Problems
44. The push-pull stage will operate nonlinearly if a diode is shorted, a transistor is faulty,
or the op-amp stage has excessive gain.
45. If a 100 kΩ resistor is used for R2, the gain of the op amp will be reduced by a factor of
100.
46. If D1 opens, the positive half of the signal will appear on the output through Q3 and Q4.
The negative half is missing due to the open diode.
Datasheet Problems
47. From the datasheet of textbook Figure 12-78:
470
B 0.0099
47 k 470
Aol 200,000 (typical)
Zin 2.0 M (typical)
Zin (NI) (1 0.0099)(200,000)(2 M) (1 1980)2 M 3.96 G
Chapter 12
48. From the datasheet in textbook Figure 12-78:
Rf 100 k
Z in (I) Ri 1 k
Acl 100
50 V 50,000 V
49. Aol 50 V/mV 50,000
1 mV 1V
50. Slew rate 0.5 V/ s
V 8 V (8 V) 16 V
16 V
t 32 s
0.5 V/ s
Advanced Problems
51. Using available standard values of R f 150 k and Ri 1.0 k,
150 k
Av 1 151
1.0 k
1.0 k
B 6.62 103
151 k
Z in (NI) (1 (6.62 103 )(50,000))300 k 99.6 M
The compensating resistor is
Rc Ri R f 150 k 1.0 k 993
See Figure 12-3.
Figure 12-3
Chapter 12
52. See Figure 12-4. 2% tolerance resistors are used to achieve a 5% gain tolerance.
Figure 12-4
53. From textbook Figure 12-79:
f c 10 kHz at Av 40 dB 100
In this circuit
33 k
Av 1 100.1 100
333
The compensating resistor is
Rc 33 k 333 330
See Figure 12-5.
Figure 12-5
54. From textbook Figure 12-80:
For a ±10 V output swing minimum, the load must be 600 Ω for a ±10 V and ≈ 620 Ω for
–10 V. So, the minimum load is 620 Ω.
Chapter 12
55. For the amplifier,
100 k
Av 50
2 k
The compensating resistor is
Rc 100 k 2 k 1.96 k 2 k
See Figure 12-6.
Figure 12-6
56. From textbook Figure 12-79 the maximum 741 closed loop gain with BW = 5 kHz is
approximately 60 dB – (20 dB)log(5 kHz/1 kHz) = 60 dB – (20 dB)(0.7) = 46 dB
Av (dB) 20log Av
Av (dB) 1 46
Av log 1 log 200
20 20
Multisim Troubleshooting Problems
57. Rf open
58. Ri open
59. Rf leaky
60. Ri shorted
61. Rf shorted
62. Op-amp input to output open
63. Rf leaky
Chapter 12
64. Ri leaky
65. Ri shorted
66. Ri open
67. Rf open
68. Rf leaky
69. Rf open
70. Rf shorted
71. Ri open
72. Ri leaky
Chapter 13
Basic Op-Amp Circuits
Section 13-1 Comparators
1. Vout ( p ) AolVin (80,000)(0.15 mV)(1.414) 17 V
Since 12 V is the peak limit, the op-amp saturates.
Vout ( pp ) 24V with distortion due to clipping.
2. (a) Maximum negative
(b) Maximum positive
(c) Maximum negative
R2 18 k
3. VUTP (10 V) 10 V 2.77 V
R1 R2 65 k
R2 18 k
VLTP (10 V) (10 V) 2.77 V
R1 R2 65 k
4. VHYS VUTP VLTP 2.77 V (2.77 V) 5.54 V
5. See Figure 13-1.
Figure 13-1
Chapter 13
R2 18 k
6. (a) VUTP
Vout ( max ) 11 V 3.88 V
R1 R2 51 k
VLTP 3.88 V
VHYS VUTP VLTP 3.88 V (3.88 V) 7.76 V
R2 68 k
(b) VUTP
Vout ( max ) 11 V 3.43 V
R1 R2 218 k
VLTP 3.43 V
VHYS VUTP VLTP 3.43 V (3.43 V) 6.86 V
7. When the zener is forward-biased:
18 k
Vout Vout 0.7 V
18 k 47 k
Vout (0.277)Vout 0.7 V
Vout (1 0.277) 0.7 V
0.7 V
Vout 0.968 V
1 0.277
When the zener is reverse-biased:
18 k
Vout Vout 6.2 V
18 k 47 k
Vout (0.277)Vout 6.2 V
Vout (1 0.277) 6.2 V
6.2 V
Vout 8.57 V
1 0.277
10 k
8. Vout Vout (4.7 V 0.7 V)
10 k 47 k
Vout (0.175)Vout 5.4 V
5.4 V
Vout 6.55 V
1 0.175
VUTP (0.175)(6.55 V) 1.15 V
VLTP (0.175)(6.55 V) 1.15 V
Chapter 13
See Figure 13-2.
Figure 13-2
Section 13-2 Summing Amplifiers
Rf
9. (a) VOUT ( 1 V 1.5 V) 1(1 V 1.5 V) 2.5 V
Ri
Rf 22 k
(b) VOUT (0.1 V 1 V 0.5 V) (1.6 V) 3.52 V
Ri 10 k
10. (a) VR1 1 V
VR2 1.8 V
1V
(b) I R1 45.5 A
22 k
1.8 V
IR 2 81.8 A
22 k
I f I R1 I R 2 45.5 A 81.8 A 127 A
(c) VOUT I f R f (127 A)(22 k) 2.8 V
Rf
11. 5Vin Vin
R
Rf
5
R
R f 5 R 5(22 k) 110 kΩ
Chapter 13
12. See Figure 13-3.
Figure 13-3
R f Rf Rf Rf
13. VOUT V1 V2 V3 V4
R1 R2 R3 R4
10 k 10 k 10 k 10 k
2 V 3 V 3 V 6 V
10 k 33 k 91 k 180 k
(2 V 0.91 V 0.33 V 0.33 V) 3.57 V
Vout 3.57 V
If 357 μA
Rf 10 k
14. R f 100 k
Input resistors: R1 100 k, R2 50 k, R3 25 k, R4 12.5 k
R5 6.25 k, R6 3.125 k
Section 13-3 Integrators and Differentiators
dVout V 5V
15. IN 4.06 mV/ μs
dt RC (56 k)(0.022 F)
16. See Figure 13-4.
Figure 13-4
Chapter 13
CV pp (0.001 F)(5 V)
17. I 1 mA
T /2 10 s / 2
V pp 2V
18. Vout RC (15 k)(0.047 F) ±2.82 V
T / 2 0.5 ms
See Figure 13-5.
Figure 13-5
19. For the 10 ms interval when the switch is in position 2:
Vout V 5V 5V
IN 50 V/s 50 mV/ms
t RC (10 k)(10 F) 0.1 s
Vout (50 mV/ms)(10 ms) 500 mV 0.5 V
For the 10 ms interval when the switch is in position 1:
Vout V 5 V 5 V
IN 50 V/s 50 mV/ms
t RC (10 k)(10 F) 0.1 s
Vout (50 mV/ms)(10 ms) 500 mV 0.5 V
See Figure 13-6
Figure 13-6
Chapter 13
Section 13-4 Troubleshooting
R2
20. VB Vout (VZ 0.7 V)
R1 R2
(VZ 0.7 V)
VB
R2
1
R1 R2
Normally, VB should be
(4.3 V 0.7 V)
VB 10 V
1 0.5
Since the negative portion of VB is only –1.4 V, zener D2 must be shorted:
(0 V 0.7 V)
VB 1.4 V
1 0.5
21. The output should be as shown in Figure 13-7. V2 has no effect on the output. This
indicates that R2 is open.
Figure 13-7
2.5 k
22. Vv 0.25
10 k
The output should be as shown in Figure 13-8. An open R2 (V2 is missing) will produce
the observed output, which is incorrect.
Figure 13-8
23. The D2 input is missing (acts as a constant 0). This indicates an open 50 k resistor.
Chapter 13
Device Application Problems
24. The first thing that you should always do is visually inspect the circuit for bad contacts or
loose connections, shorts from solder splashes or wire clippings, incorrect components,
and incorrectly installed components. After careful inspection, you have found nothing
wrong. Measurements are now necessary to isolate a component’s fault.
25. An open decoupling capacitor can make the circuit more susceptible to power line noise.
26. If a 1.0 k resistor is used for R1, the inverting input would be increased, causing the
pulse width to narrow for a given setting of the potentiometer.
Advanced Problems
24 V
27. I R1-2-3 39.2 A
612 k
Minimum setting of R2:
VINV 12 V (39.2 A)(56 k) 9.8 V
v V p sin
v 9.8 V
sin 0.98
V p 10 V
v
sin 1 sin 1 (0.98) 78.5 (on positive half cycle)
Vp
Angle from 78.5 to 90
90 78.5 11.5
Angle from 90 to next point at which v 9.8 V:
11.5
Angle from first point at which v = 9.8 V to second point at which v = 9.8 V on sine wave is
11.5 11.5 23
23
min. duty cycle 100 6.39%
360
See Figure 13-9(a).
Maximum setting of R2:
VINV 12 V (39.2 A)(556 k) 9.8 V
v 9.8 V
sin 78.5 (on negative half cycle)
Vp 10 V
Chapter 13
360 23
max. duty cycle 100 93.6%
360
See Figure 13-9(b).
(a)
(b)
Figure 13-9
28. Let VINV 4.8 V
Let I1 39.2 A
VINV 12 V I1R1
I1R1 4.8 V 12 V
I1R1 7.2 V
7.2 V
R1 184 k
39.2 A
Change R1 and R3 to 184 k .
29. 100 mV/s 5 V/Ri C
5V
Ri C
100 mV/ s
Chapter 13
For C 3300 pF :
50 s
Ri 15.15 k 15 k 150
3300 pF
For a 5 V peak-peak triangle waveform:
5V
tramp up tramp down 50 s
100 mV/ s
2(50 s) 100 s
fin 1/100 s 100 kHz
See Figure 13-10.
Figure 13-10
Multisim Troubleshooting Problems
30. R1 open
31. Op-amp inputs shorted together
32. Op-amp + input to output shorted
33. D1 shorted
34. Top 10 k resistor open
35. Middle 10 k resistor shorted
36. Rf leaky
37. Rf open
38. C leaky
39. C open
Chapter 14
Special-Purpose Integrated Circuits
Section 14-1 Instrumentation Amplifiers
R1 100 k
1. Av (1) 1 1 101
RG 1.0 k
R2 100 k
Av (2) 1 1 101
RG 1.0 k
2R 200 k
2. Acl 1 1 201
RG 1.0 k
3. Vout Acl (Vin 2 Vin1 ) 202(10 mV 5 mV) 1.005 V
2R
4. Av 1
RG
2R
Av 1
RG
2R 2(100 k) 200 k
RG 200.2 200 Ω
Av 1 1000 1 999
50.5 k
5. RG
Av 1
50.5 k
Av 1 51.5
1.0 k
6. Using the graph in textbook Figure 14-6,
BW 300 kHz
7. Change RG to
50.5 k 50.5 k
RG 2.2 kΩ
Av 1 24 1
50.5 k 50.5 k
8. RG 2.7 kΩ
Av 1 20 1
Chapter 14
Section 14-2 Isolation Amplifiers
9. Av (total ) (30)(10) 300
Rf 1 18 k
10. (a) Av1 1 1 3.2
Ri1 8.2 k
Rf 2 150 k
Av 2 1 1 11
Ri 2 15 k
Av (tot ) Av1 Av 2 (3.2)(11) 35.2
Rf1 330 k
(b) Av1 1 1 331
Ri1 1.0 k
Rf 2 47 k
Av 2 1 1 4.13
Ri 2 15 k
Av (tot ) Av1 Av 2 (331)(4.13) 1367
11. Av 2 11 (from Problem 10(a))
Av1 Av 2 100
Rf1 100
1 Av1 9.09
Ri1 11
R f 1 (9.09 1) Ri1 (8.09)(8.2 k) 66 k
Change R f (18 k) to 66 k.
Use 68 k 1% standard value resistor.
12. Av1 331 (from Problem 10(b))
Av1 Av 2 440
Rf 2 440
1 Av 2 1.33
Ri 2 331
Change R f (47 k) to 3.3 k.
Change Ri (15 k) to 10 k.
13. Connect pin 6 to pin 10 and pin 14 to pin 15. Make R f 0.
Chapter 14
Section 14-3 Operational Transconductance Amplifiers (OTAs)
I out 10 A
14. gm 1 mS
Vin 10 mV
15. I out g mVin (5000 S)(100 mV) 500 μA
Vout I out RL (500 A)(10 k) 5 V
I out
16. gm
Vin
I out g mVin (4000 S)(100 mV) 400 A
Vout 3.5 V
RL 8.75 kΩ
I out 400 A
12 V (12 V) 0.7 V 12 V (12 V) 0.7 V 23.3 V
17. I BIAS 106 A
RBIAS 220 k 220 k
From the graph in Figure 14-59:
g m KI BIAS (16 S/ A)(106 A) 1.70 mS
Vout I out RL
Av g m RL (1.70 mS)(6.8 k) 11.6
Vin Vin
18. The maximum voltage gain occurs when the 10 k potentiometer is set to 0 and was
determined in Problem 17.
Av (max) 11.6
The minimum voltage gain occurs when the 10 k potentiometer is set to 10 k .
12 V (12 V) 0.7 V 23.3 V
I BIAS 101 A
220 k 10 k 230 k
g m (16 S/ A)(101 A) 1.62 mS
Av (min) g m RL (1.62 mS)(6.8 k) 11.0
19. The VMOD waveform is applied to the bias input.
The gain and output voltage for each value of VMOD is determined as follows using
K 16S/ A. The output waveform is shown in Figure 14-1.
For VMOD 8 V :
8 V ( 9 V) 0.7 V 16.3 V
I BIAS 418 A
39 k 39 k
Chapter 14
g m KI BIAS (16 S/ A)(418 A) 6.69 mS
Vout I out RL
Av g m RL (6.69 mS)(10 k) 66.9
Vin Vin
Vout AvVin (66.9)(100 mV) 6.69 V
For VMOD 6 V:
6 V ( 9 V) 0.7 V 14.3 V
I BIAS 367 A
39 k 39 k
g m KI BIAS (16 S/ A)(367 A) 5.87 mS
Vout I out RL
Av g m RL (5.87 mS)(10 k) 58.7
Vin Vin
Vout AvVin (58.7)(100 mV) 5.87 V
For VMOD 4 V :
4 V ( 9 V) 0.7 V 12.3 V
I BIAS 315 A
39 k 39 k
g m KI BIAS (16 S/ A)(315 A) 5.04 mS
Vout I out RL
Av g m RL (5.04 mS)(10 k) 50.4
Vin Vin
Vout AvVin (50.4)(100 mV) 5.04 V
For VMOD 2 V :
2 V (9 V) 0.7 V 10.3 V
I BIAS 264 A
39 k 39 k
g m KI BIAS (16 S/ A)(264 A) 4.22 mS
Vout I out RL
Av g m RL (4.22 mS)(10 k) 42.2
Vin Vin
Vout AvVin (42.2)(100 mV) 4.22 V
For VMOD 1 V :
1 V (9 V) 0.7 V 9.3 V
I BIAS 238 A
39 k 39 k
g m KI BIAS (16 S/ A)(238 A) 3.81 mS
Vout I out RL
Av g m RL (3.81 mS)(10 k) 38.1
Vin Vin
Vout AvVin (38.1)(100 mV) 3.81 V
Chapter 14
Figure 14-1
9V (9 V) 0.7 V 17.3 V
20. I BIAS 444 A
39 k 39 k
VTRIG( ) I BIAS R1 (444 A)(10 k) +4.44 V
VTRIG( ) I BIAS R1 (444 A)(10 k) 4.44 V
21. See Figure 14-2.
Figure 14-2
Chapter 14
Section 14-4 Log and Antilog Amplifiers
22. (a) ln(0.5) 0.693
(b) ln(2) = 0.693
(c) ln(50) = 3.91
(d) ln(130) = 4.87
23. (a) log10(0.5) = –0.301
(b) log10(2) = 0.301
(c) log10(50) = 1.70
(d) log10(130) = 2.11
24. Antilog x 10 x or ex, depending on the base used.
INV ln e1.6 4.95
INV log 101.6 39.8
25. The output of a log amplifier is limited to 0.7 V because the output voltage is limited to
the barrier potential of the transistor’s pn junction.
V
26. Vout (0.025 V) ln in
I s Rin
3V
(0.025 V)ln (0.025 V)ln(365.9) 148 mV
(100 nA)(82 k)
Vin
27. Vout (0.025 V)ln
I EBO Rin
1.5 V
(0.025V) ln (0.025 V)ln(531.9) 157 mV
(60 nA)(47 k)
Vin
V
28. Vout R f I EBO antilog in R f I EBO e 25 mV
25 mV
0.225 V
Vout (10 k)(60 nA)e 25 mV (10 k)(60 nA)e9 (10 k)(60 nA)(8103) 4.86 V
Vin 1V
29. Vout ( max ) (0.025 V)ln (0.025 V ln
I EBO Rin (60 nA(47 k)
(0.025 V) ln(354.6) 147 mV
Vin 100 mV
Vout ( min ) (0.025 V) ln (0.025 V) ln
I EBO Rin (60 nA)(47 k)
(0.025 V) ln(35.5) 89.2 mV
The signal compression allows larger signals to be reduced without causing smaller
amplitudes to be lost (in this case, the 1 V peak is reduced 85% but the 100 mV peak is
reduced only 10%).
Chapter 14
Section 14-5 Converters and Other Integrated Circuits
30. (a) VIN VZ 4.7 V
VIN 4.7 V
IL 4.7 mA
Ri 1.0 k
10 k
(b) VIN 12 V 6 V
20 k
Ri 10 k 10 k 100 5.1 k
VIN 6V
IL 1.18 mA
Ri 5.1 k
31. See Figure 14-3.
Figure 14-3
Multisim Troubleshooting Problems
32. RG leaky
33. R open
34. Rf open
35. Zener diode open
36. Lower 10 k resistor open
Chapter 15
Active Filters
Section 15-1 Basic Filter Responses
1. (a) Band-pass
(b) High-pass
(c) Low-pass
(d) Band-stop
2. BW f c 800 Hz
1 1
3. fc 48.2 Hz
2 RC 2 (2.2 k)(0.0015 F)
No, the upper response roll-off due to internal device capacitances is unknown.
4. The roll-off is 20 dB/decade because this is a single-pole filter.
5. BW f c 2 fc1 3.9 kHz 3.2 kHz 0.7 kHz 700 Hz
f0 f c1 f c 2 (3.2 kHz)(3.9 kHz) 3.53 kHz
f0 3.53 kHz
Q 5.04
BW 700 Hz
f0
6. Q
BW
f0 Q( BW ) 15(1 kHz) 15 kHz
Section 15-2 Filter Response Characteristics
7. (a) 2nd order, 1 stage
R3 1.2 k
DF 2 2 2 1 1 Not Butterworth
R4 1.2 k
(b) 2nd order, 1 stage
R3 560
DF 2 2 2 0.56 1.44 Approximately Butterworth
R4 1.0 k
Chapter 15
(c) 3rd order, 2 stages, 1st stage (2 poles):
R3 330
DF 2 2 1.67
R4 1.0 k
2nd stage (1 pole):
R6
DF 2 1.67 Not Butterworth
R7
8. (a) and (c) are low-pass; (b) is high-pass.
9. (a) and (b) are two-pole filters with approximately a –40 dB/decade roll-off. (c) is a
three-pole filter with approximately a –60 dB/decade roll-off rate.
10. (a) From Table 15-1 in the textbook, the damping factor must be 1.414; therefore,
R3
0.586
R4
R3 0.586 R4 0.586(1.2 k) 703
Nearest standard value: 720 Ω
R3
(b) 0.56
R4
This is an approximate Butterworth response
(as close as you can get using standard 5% resistors).
(c) From Table 15-1, the damping factor of both stages must be 1, therefore
R3
1
R4
R3 R4 R6 R7 1 k (for both stages)
11. (a) Chebyshev
(b) Butterworth
(c) Bessel
(d) Butterworth
Section 15-3 Active Low-Pass Filters
12. High Pass
1st stage:
R3 1.0 k
DF 2 2 1.85
R4 6.8 k
Chapter 15
2nd stage:
R7 6.8 k
DF 2 2 0.786
R8 5.6 k
From Table 15-1 in the textbook:
1st stage DF = 1.848 and 2nd stage DF = 0.765
Therefore, this filter is approximately Butterworth.
Roll-off rate = 80 dB/decade
1 1 1
13. fc 190 Hz
2 R1 R2 C1C2 2 R5 R6C3C4 2 (4.7 k)(6.8 k)(0.22 F)(0.1 F)
14. R R1 R2 R5 R6 and C C1 C2 C3 C4
Let C 0.22 F (for both stages).
1 1
fc
2 R C 2 2 2 RC
1 1
R 3.81 k
2 f c C 2 (190 Hz)(0.22 F)
Choose R = 3.9 kΩ (for both stages)
15. Add another identical stage and change the ratio of the feedback resistors to 0.068 for
first stage, 0.586 for second stage, and 1.482 for third stage. See Figure 15-1.
Figure 15-1
Chapter 15
16. See Figure 15-2.
Figure 15-2
Section 15-4 Active High-Pass Filters
17. Exchange the positions of the resistors and the capacitors. See Figure 15-3.
Figure 15-3
1
18. fc
2 RC
190 Hz
f0 95 Hz
2
Chapter 15
1 1
R 7615
2 f c C 2 (95 Hz)(0.22 F)
Let R = 7.5 kΩ. Change R1, R2, R5 and R6 to 7.5 kΩ.
19. (a) Decrease R1 and R2 or C1 and C2.
(b) Increase R3 or decrease R4.
Section 15-5 Active Band-Pass Filters
20. (a) Cascaded high-pass/low-pass filters
(b) Multiple feedback
(c) State variable
21. (a) 1st stage:
1 1
f c1 3.39 kHz
2 RC 2 (1.0 k)(0.047 F)
2nd stage:
1 1
fc 2 7.23 kHz
2 RC 2 (1.0 k)(0.022 F)
f0 f c1 f c 2 (3.39 kHz)(7.23 kHz) 4.95 kHz
BW 7.23 kHz 3.39 Hz 3.84 kHz
1 R1 R3 1 47 k 1.8 k
(b) f0 449 Hz
2 C R1R3 R2 2 (0.022 F) (47 k)(1.8 k)(150 k)
Q f 0CR2 (449 Hz)(0.022 F)(150 k) 4.66
f 0 449 Hz
BW 96.4 Hz
Q 4.66
(c) For each integrator:
1 1
fc 15.9 kHz
2 RC 2 (10 k)(0.001 F)
f 0 f c 15.9 kHz
1 R 1 560 k 1
Q 5 1 1 (56 1) 19
3 R6 3 10 k 3
f 0 15.9 kHz
BW 838 Hz
Q 19
Chapter 15
1 R
22. Q 5 1
3 R6
Select R6 = 10 kΩ.
R5 1 R5 R6
Q
3R6 3 3R6
3R6Q R5 R6
R5 3R6Q R6 3(10 k)(50) 10 k 1500 k 10 k 1490 k
1
f0 1.33 kHz
2 (12 k)(0.01 F)
f 0 1.33 kHz
BW 26.6 Hz
Q 50
Section 15-6 Active Band-Stop Filters
23. See Figure 15-4.
Figure 15-4
1
24. f0 fc
2 RC
Let C remain 0.01 μF.
1 1
R 133 k
2 f 0C 2 (120 Hz)(0.01 F)
Change R in the integrators from 12 kΩ to 133 kΩ.
Chapter 15
Multisim Troubleshooting Problems
25. R4 shorted
26. R3 open
27. C3 shorted
28. R5 open
29. R1 open
30. R2 shorted
31. R1 open
32. C2 open
33. R7 open
Chapter 16
Oscillators
Section 16-1 The Oscillator
1. An oscillator requires no input other than the dc supply voltage.
2. Amplifier and positive feedback circuit
Section 16-2 Feedback Oscillators
3. Unity gain around the closed loop is required for sustained oscillation.
Acl Av B 1
1 1
B 0.0133
Av 75
4. To ensure startup:
Acl 1
since Av 75, B must be greater than 1/75 in order to produce the condition
Av B 1.
For example, if B 1/ 50,
1
Av B 75 1.5
50
Section 16-3 Oscillators with RC Feedback Circuits
Vout 1
5.
Vin 3
1 2.2 V
Vout Vin 733 mV
3 3
1 1
6. fr 1.28 kHz
2 RC 2 (6.2 k)(0.02 F)
Chapter 16
1 1
7. f r ( min ) 249 Hz
2 R( max )C 2 (6.4 k)(0.1 F)
1 1
f r ( max ) 270 Hz
2 R( min )C 2 (5.9 k)(0.1 F)
R1 R2 R1
8. Acl 1
R2 R2
R1 R2 ( Acl 1)
Substitute R f R1 ; R2 Rlamp and solve for R f :
R f Rlamp ( ACL 1) 160 (3 1) 320 Ω
9. R f ( Av 1)( R3 rds ) (3 1)(820 350 ) 2.34 k
1
10. fr 10.6 kHz
2 (1.0 k)(0.015 F)
1
11. B
29
1
Acl 29
B
Rf
Acl
Ri
R f Acl Ri 29(4.7 k) 136 k
1
fr 628 Hz
2 6(4.7 k)(0.022 F)
Section 16-4 Oscillators with LC Feedback Circuits
12. (a) Colpitts: C1 and C3 are the feedback capacitors.
1
fr
2 L1CT
C1C3 (100 F)(1000 pF)
CT 90.9 pF
C1 C3 1100 pF
1
fr 236 kHz
2 (5 mH)90.9 pF)
Chapter 16
(b) Hartley:
1
fr
2 LT C2
LT L1 L2 1.5 mH 10 mH 11.5 mH
1
fr 68.5 kHz
2 (11.5 mH)(470 pF)
47 pF
13. B 0.1
470 pF
The condition for sustained oscillation is
1 1
Av 10
B 0.1
Section 16-5 Relaxation Oscillators
14. Triangular waveform.
1 R2 1 56 k
f 1.61 kHz
4 R1C R3 4(22 k)(0.22 F) 18 k
15. Change f to 10 kHz by changing R1:
1 R2
f
4 R1C R3
1 R2 1 56 k
R1 3.54 k
4 fC R3 4(10 kHz)(0.022 F) 18 k
V p VF
16. T
VIN
RC
R5 47 k
Vp 12 V 12 V 3.84 V
R4 R5 147 k
PUT triggers at about +3.84 V (ignoring the 0.7 V drop)
Amplitude = +3.84 V – 1 V = 2.84 V
R2 22 k
VIN (12 V) (12 V) 2.16 V
R1 R2 122 k
Chapter 16
3.84 V 1 V
T 289 s
2.16 V
(100 k)(0.0022 F)
1 1
f 3.46 kHz
T 289 s
See Figure 16-1.
Figure 16-1
17. VG 5 V. Assume VAK 1 V.
R5 47 k
R5
VG 12 V
R4 R5
Change R4 to get VG = 5 V.
5V(R4 47 k) (47 k)12 V
R4 (5V) (47 k)12 V (47 k)5 V
(12 V 5 V)47 k
R4 65.8 k
5V
V p VF
18. T
VIN
RC
V 3V
V p IN T VF 10 s 1 V 7.38 V
RC (4.7 k)(0.001 F)
V pp ( out ) V p VF 7.38 V 1 V 6.38 V
Chapter 16
Section 16-6 The 555 Timer as an Oscillator
1 1
19. VCC (10 V) 3.33 V
3 3
2 2
VCC (10 V) 6.67 V
3 3
1.44 1.44
20. f 4.03 kHz
( R1 2 R2 )Cext (1.0 k 6.6 k)(0.047 F)
1.44
21. f
( R1 2 R2 )Cext
1.44 1.44
Cext 0.0076 F
( R1 2 R2 ) f (1.0 k 6.6 k)(25 kHz)
R1 R2
22. Duty cycle (dc) 100%
R1 2 R2
dc(R1 2R2 ) ( R1 R2 )100
75(3.3 k 2R2 ) (3.3 k R2 )100
75(3.3 k) 150R2 100(3.3 k) 100R2
150R2 100R2 100(3.3 k) 75(3.3 k)
50R2 25(3.3 k)
25(3.3 k)
R2 1.65 k
50
Multisim Troubleshooting Problems
23. Drain-to-source shorted
24. C3 open
25. Collector-to-emitter shorted
26. R1 open
27. R2 open
28. R1 leaky
Chapter 17
Voltage Regulators
Section 17-1 Voltage Regulation
V 2 mV
1. Percent line regulation OUT 100% 100% 0.0333%
VIN 6V
V V 2 mV 8 V
2. Percent line regulation OUT OUT 100% 100% 0.00417% / V
VIN 6V
V V 10 V 9.90 V
3. Percent load regulation NL FL 100% 100% 1.01%
VFL 9.90 V
4. From Problem 3, the percent load regulation is 1.01%. For a full load current of 250 mA,
this can be expressed as
1.01%
0.00404% / mA
250 mA
Section 17-2 Basic Linear Series Regulators
5. See Figure 17-1.
Figure 17-1
R 33 k
6. VOUT 1 2 VREF 1 2.4 V 10.3 V
R3 10 k
R 5.6 k
7. VOUT 1 2 VREF 1 2.4 V 8.51 V
R3 2.2 k
Chapter 17
8. For R3 = 2.2 kΩ:
R 5.6 k
VOUT 1 2 VREF 1 2.4 V 8.5 V
R3 2.2 k
For R3 = 4.7 kΩ:
R 5.6 k
VOUT 1 2 VREF 1 2.4 V 5.26 V
R3 4.7 k
The output voltage decreases by 3.24 V when R3 is changed from 2.2 kΩ to 4.7 kΩ.
R 5.6 k
9. VOUT 1 2 VREF 1 2.7 V 9.57 V
R3 2.2 k
0.7 V
10. I L(max)
R4
0.7 V 0.7 mA
R4 2.8
I L(max) 250 mA
2
P I L(max) R4 (250 mA) 2 2.8 0.175 W. Use a 0.25 W.
2.8
11. R4 1.4
2
0.7 V 0.7 V
I L(max) 500 mA
R4 1.4
Section 17-3 Basic Linear Shunt Regulators
12. Q1 conducts more when the load current increases, assuming that the output voltage
attempts to increase. When the output voltage tries to increase due to a change in load
current, the attempted increase is sensed by R3 and R4 and a proportional voltage is
applied to the op-amp’s non-inverting input. The resulting difference voltage increases
the op-amp output, driving Q1 more and thus increasing its collector current.
VR1 1V
13. I C 10 mA
R1 100
R 10 k
14. VOUT 1 3 VREF 1 5.1 V 18.2 V
R4 3.9 k
VOUT 18.2 V
I L1 18.2 mA
RL1 1 k
VOUT 18.2 V
I L2 15.2 mA
RL2 1.2 k
Chapter 17
I L 15.2 mA 18.2 mA 3.0 mA
IS I L 3.0 mA
VIN 25 V
15. I L(max) 250 mA
R1 100
2
PR1 I L(max) R1 (250 mA) 2100 6.25 W
Section 17-4 Basic Switching Regulators
t
16. VOUT on VIN
T
ton T toff
1 1
T 0.0001 s 100 s
f 10 kHz
40 s
VOUT 12 V 4.8 V
100 s
17. f 100 Hz, toff 6 ms
1 1
T 10 ms
f 100 Hz
ton T toff 10 ms 6 ms 4 ms
ton 4 ms
duty cycle 0.4
T 10 ms
percent duty cycle 0.4 100% 40%
18. The diode D1 becomes forward-biased when Q1 turns off.
19. The output voltage decreases.
Section 17-5 Integrated Circuit Voltage Regulators
20. (a) 7806: +6 V
(b) 7905: –5.2 V
(c) 7818: +18 V
(d) 7924: –24 V
R 10 k
21. VOUT 1 2 VREF I ADJ R2 1 1.25 V (50 A)(10 k)
R1 1.0 k
13.7 V 0.5 V 14.3 V
Chapter 17
R2( min )
22. VOUT(min) 1 VREF I ADJ R2( min )
R1
R2( min ) 0
VOUT( min ) (1.25 V(1+0)+0) 1.25 V
R2( max ) 10 k
VOUT(max) 1 VREF I ADJ R2( max ) 1.25 V 1+ (50 A)(10 k)
R1 470
1.25 V(22.28)+0.5 V 28.4 V
23. The regulator current equals the current through R1 + R2.
VOUT 14.3 V
I REG 1.3 mA
R1 R2 11 k
24. VIN 18 V, VOUT 12 V
I REG(max) 2 mA, VREF 1.25 V
VREF 1.25 V
R1 625
I REG 2 mA
Neglecting IADJ:
VR2 12 V 1.25 V 10.8 V
VR2 10.8 V
R2 5.4 k
I REG 2 mA
For R1 use 620 Ω and for R2 use either 5600 Ω or a 10 kΩ potentiometer for precise
adjustment to 12 V.
Section 17-6 Integrated Circuit Voltage Regulator Configurations
25. VRext (min) 0.7 V
0.7 V 0.7 V
Rext 2.8
I max 250 mA
26. VOUT 12 V
12 V
IL 1200 mA 1.2 A
10
I ext I L I max 1.2 A 0.5 A 0.7 A
Pext I ext (VIN VOUT ) 0.7 A(15 V 12 V) 0.7 A(3 V) 2.1 W
Chapter 17
27. VRlim ( min ) 0.7 V
0.7 V 0.7 V
Rlim ( min ) 0.35
I ext 2A
See Figure 17-2.
Figure 17-2
1.25 V
28. R 2.5
500 mA
See Figure 17-3.
Figure 17-3
29. I 500 mA
8V
R 16
500 mA
See Figure 17-4.
Figure 17-4
30. Connect pin 7 to pin 6.
Chapter 17
Multisim Troubleshooting Problems
The solutions showing instrument connections for Problems 31 through 34 are available from the
Instructor Resource Center. See Chapter 2 for instructions. The faults in the circuit files may be
accessed using the password book (all lowercase).
31. R2 leaky
32. Zener diode open
33. Q2 collector-to-emitter open
34. R1 open
Chapter 18
Communication Devices
and Methods
Section 18-1 Basic Receivers
1. See Figure 18-1.
Figure 18-1
2. See Figure 18-2.
Figure 18-2
3. f LO 680 kHz 455 kHz 1135 kHz
4. f LO 97.2 MHz 10.7 MHz 107.9 MHz
Chapter 18
5. f RF 101.9 MHz 10.7 MHz 91.2 MHz
f IF 10.7 MHz (always)
Section 18-2 The Linear Multiplier
6. (a) Vout 2.5 V
(b) Vout 1.6 V
(c) Vout 1.0 V
(d) Vout 10 V
7. Vout KVX VY 0.125(3.5 V)(2.9 V) 1.27 V
8. Connect the two inputs together.
9. (a) Vout KV1V2 (0.1)(2 V)( 1.4 V) 0.28 V
(b) Vout KV1V2 KV12 (0.1)(3.2 V) 2 1.024 V
V1 (6.2 V)
(c) Vout 2.07 V
V2 3 V
(d) Vout V1 6.2 V 2.49 V
Section 18-3 Amplitude Modulation
10. f diff f1 f 2 100 kHz 30 kHz 70 kHz
f sum f1 f 2 100 kHz 30 kHz 130 kHz
9 cycles
11. f1 9000 cycles/s 9 kHz
1 ms
1 cycles
f2 1000 cycles/s 1 kHz
1 ms
f diff f1 f 2 9 kHz 1 kHz 8 kHz
f sum f1 f 2 9 kHz 1 kHz 10 kHz
12. fc 1000 kHz
f diff 1000 kHz 3 kHz 997 kHz
f sum 1000 kHz 3 kHz 1003 kHz
Chapter 18
18 cycles
13. f1 1.8 MHz
10 s
1 cycles
f2 100 kHz
10 s
f diff f1 f 2 1.8 MHz 100 kHz 1.7 MHz
f sum f1 f 2 1.8 MHz 100 kHz 1.9 MHz
fc 1.8 MHz
14. fc 1.2 MHz by inspection
f m f c f diff 1.2 MHz 1.1955 MHz 4.5 kHz
f diff f sum 847 kHz 853 KHz
15. fc 850 kHz
2 2
f m f c f diff 850 kHz 847 kHz 3 kHz
16. f diff ( min ) 600 kHz 3 kHz 597 kHz
f diff ( max ) 600 kHz 300 Hz 599.7 kHz
f sum ( min ) 600 kHz 300 kHz 600.3 kHz
f sum ( max ) 600 kHz 3 kHz 603 kHz
See Figure 18-3.
Figure 18-3
Chapter 18
Section 18-4 The Mixer
1
17. (sin A)(sin B ) [cos( A B ) cos( A B)]
2
Vin (1) 0.2 V sin [2 (2200 kHz)t ]
Vin (2) 0.15 V sin [2 (3300 kHz)t ]
Vin (1)Vin (2) (0.2 V)(0.15 V) sin [2 (2200 kHz)t ] sin [2 (3300 kHz)t ]
(0.2 V)(0.15 V)
Vout [cos 2 (3300 kHz 2200 kHz)t cos 2 (3300 kHz 2200 kHz)t ]
2
Vout 15 mVcos [2 (1100 kHz)t ] 15 mV cos [2 (5500 kHz)t ]
18. f IF f LO fc 986.4 kHz 980 kHz 6.4 kHz
Section 18-5 AM Demodulation
19. See Figure 18-4.
Figure 18-4
20. See Figure 18-5.
Figure 18-5
Chapter 18
21. See Figure 18-6.
Figure 18-6
Section 18-6 IF and Audio Amplifiers
22. fc f m 1.2 MHz 8.5 kHz 1.1915 MHz
fc f m 1.2 MHz 8.5 kHz 1.2085 MHz
fc 1.2 MHz
f LO f m 455 kHz 8.5 kHz 446.5 kHz
f LO f m 455 kHz 8.5 kHz 463.5 kHz
f LO 455 kHz
23. The IF amplifier has a 450 kHz to 460 kHz passband.
The audio/power amplifiers have a 10 Hz to 5 kHz bandpass.
Section 18-7 Frequency Modulation
24. An FM signal differs from an AM signal in that the information is contained in frequency
variations of the carrier rather than amplitude variations.
25. Varactor
Chapter 18
Section 18-8 The Phase-Locked Loop (PLL)
26. See Figure 18-7.
Figure 18-7
27. (a) The VCO signal is locked onto the incoming signal and therefore its frequency is
equal to the incoming frequency of 10 MHz.
ViVo (250 mA)(400 mV)
(b) Vc cos e cos(30 15) (0.050)(0.966) 48.3 mV
2 2
28. fo +3.6 kHz, Vc 0.5 V
f o 3.6 kHz
K 7.2 kHz / V
Vc 0.5 V
29. K 1.5 kHz/V, Vc 0.67 V
f o
K
Vc
fo K Vc (1.5 kHz/V)(+0.67 V) 1005 Hz
Section 18-9 Fiber Optics
30. The light ray will be reflected because the angle of incidence (30°) is greater than the
critical angle (15°).
31. C cos 1 (n2 /n1 ) cos 1 (1.25/1.55) 36.2
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