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Vel Tech: 1150EC101 - Basic Electronics Engineering

This document contains information about a course on basic electronics engineering taught by Mr. A. Sasikar at Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology in Chennai, India. It includes definitions and explanations of field effect transistors (FETs) and junction field effect transistors (JFETs). Specifically, it discusses the construction, symbols, and working mechanisms of n-channel JFETs, including how varying the gate-source voltage and drain-source voltage affects the depletion region width and resulting drain current. It also provides comparisons of JFETs to bipolar junction transistors (BJTs).

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Asst.Prof, EEE Veltech, Chennai
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68 views14 pages

Vel Tech: 1150EC101 - Basic Electronics Engineering

This document contains information about a course on basic electronics engineering taught by Mr. A. Sasikar at Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology in Chennai, India. It includes definitions and explanations of field effect transistors (FETs) and junction field effect transistors (JFETs). Specifically, it discusses the construction, symbols, and working mechanisms of n-channel JFETs, including how varying the gate-source voltage and drain-source voltage affects the depletion region width and resulting drain current. It also provides comparisons of JFETs to bipolar junction transistors (BJTs).

Uploaded by

Asst.Prof, EEE Veltech, Chennai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Vel Tech

Rangarajan Dr.Sagunthala
R & D Institute of Science and Technology
(Deemed to be University Estd u/s 3 of UGC Act, 1956)

1150EC101 – Basic Electronics Engineering


Faculty
Mr. A.Sasikar
Asst.Prof / ECE
Vel Tech Rangarajan Dr.Sagunthala R & D Institute of Science and
Technology,
Avadi, Chennai, INDIA.
FET
FET – Field Effect Transistor
- three layer semiconductor device

- has three terminals (Regions)

- Source (S), Drain (D) & Gate (G)

o G – Heavily doped
o S & D – Lightly doped

- Unipolar device - current conduction is due majority charge carriers


[either e –ns or holes].

- Voltage controlled device


FET Classification
FET – Water Analogy
JFET – Junction Field Effect Transistor
 two types, n-channel and p-channel

n-channel

Construction Symbol
Continued…

p-channel

Construction Symbol
Working of n-channel JFET
(i) VGS = 0 & VDS is positive
(ii) VGS < 0 & VDS is positive
(iii) VGS > 0 & VDS is positive
(i) VGS = 0 & Varying VDS (VDD)
- No variation in the width of
depletion region.
- Drain current (ID) increases as
VDS increases
-
(ii) VGS < 0 & Varying VDS (VDD)
- width of depletion region increases as VGS increases. (reverse biased)
- Drain current (ID) decreases as VDS increases with increase in VGS since channel width
decreases.
- at VGS=VP , depletion regions touches each other, blocks the current flow though channel,
hence ID becomes zero. (no conductive path)
- switched OFF.
- to switch OFF an n-channel device requires a negative gate-source voltage (VGS). Conversely,
to switch OFF a p-channel device requires positive VGS.
- where VP  Pinch off voltage

at lower VGS at VP 


(ii) VGS > 0 & Varying VDS (VDD)
- width of depletion region decreases as VGS increases. (forward biased)
- Drain current (ID) increases as VDS increases with increase in VGS since channel width
increases.
- switched ON
- to switch ON an n-channel device requires a positive gate-source voltage (VGS). Conversely,
to switch On a p-channel device requires negative VGS.
Drain Current (ID)

IDSS  drain current when VGS=0 V


Characteristics of JFET
Ohmic region

Saturation region

Cut off region

Transfer Characteristics Drain Characteristics


Comparison between JFET & BJT
Thank
Q

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