VLSI Design and Verification
VLSI Design and Verification
and
Verification
INDUSTRIAL TRAINING
PRESENTATION
Introduction
Welcome to the world of VLSI (Very Large Scale Integration) design and verification! VLSI plays a
pivotal role in modern electronics, enabling the integration of millions or even billions of transistors on
a single chip.
In essence, VLSI design involves the creation of complex semiconductor circuits, while verification
ensures these circuits function as intended. The ever-growing demand for smaller, more efficient, and
powerful electronic devices underscores the critical importance of VLSI in technological
advancements.
Today, we'll explore the fundamentals of VLSI design and verification, delving into the intricacies of
creating high-performance integrated circuits and ensuring their reliability. So, buckle up as we
embark on this journey into the heart of digital innovation!
Verilog History
•Developed by Gateway Design Automation in the mid-1980s
Gate-Level Modeling:
•Describes the system using logic gates.
•Supports various FPGA families, including Intel's Stratix, Arria, and Cyclone series.
•Includes a user-friendly GUI (Graphical User Interface) for design entry and visualization.
•Integrates with the Qsys system integration tool for IP (Intellectual Property) integration.
•Supports various HDLs (Hardware Description Languages) like Verilog, VHDL, and SystemVerilog.
Software Required
ModelSim
• Developed by Mentor Graphics (now part of Siemens).
• Aims to provide a seamless connection and data transfer between AHB master devices and APB slave
devices.
• Involves the creation of modules or components that facilitate the conversion and data exchange between
AHB and APB
• AHB Master - Implements the AHB master interface to initiate transactions on the AHB side of the
bridge.
• AHB Slave - Implements the APB slave interface to respond to transactions initiated by the AHB master.
AHB2APB Design Project
•Addresses challenges related to clock domain crossing between the AHB and APB domains.
•Involves thorough testing to ensure correct functionality and compliance with AHB and APB
specifications
•Designed with scalability in mind to accommodate various AHB and APB configurations and
requirements.
•Adheres to AMBA specifications and industry standards for bus interconnects.
•Evaluates and measures the bridge's performance in terms of latency, throughput, and overall
efficiency.
Conclusion
The AHB2APB bridges the gap between AHB and APB. It buffers the AHB's address, controls, and
data, drives the APB peripherals, and sends data and a response signal back to the AHB.
The development of the synthesizable AHB to APB Bridge in verilog HDL was done. The HCLK and
PENABLE mechanism was implemented for making it the low-power consuming system. The
functional verification of the bridge was done by driving various testcases to the design for testing the
features. The multimaster and multislave AHB to APB bridge is one of the future scope.
THANKYOU
PRESENTED BY
ABHISHEK DABAS