Module 2: Combinational logic circuit design

Combinational logic circuit design:, Karnaugh map simplification, Don’t

care conditions, , Simplification by QuineMcCluskey method,
Determination of Prime implicants, Simplification using map-entered
variables, Gate delays and Timing diagrams, Hazard and Hazard covers,
Introduction to HDL: Verilog HDL, Describing input/output, writing
module body, HDL Implementation models.
A pair eliminates one variable and
its complement.
Simplification of k-map
•The Karnaugh map uses the following rules for the simplification of
expressions by grouping together adjacent cells containing ones.
•After drawing a Kamaugh map,
●Encirclethe octets first,
●The quads second, and
●The pairs last.
Simplification of k-map
Groups may not include any cell containing a zero.
Groups may be horizontal or vertical, but not diagonal.
•Groups must contain 1, 2, 4, 8, or in general 2 n cells.

•That is if n = 1, a group will contain two 1's since 2 1 = 2.

•If n = 2, a group will contain four 1's since 2 2 = 4.

Simplification of k-map
Examples

Using K- Map simplify Y =F(A,B,C,D)= ∑m(1,2,3,6,8,9,10,12,13,14)

Groups may overlap.
Overlapping groups
Rolling the map
Groups may wrap (Rolling the Map) around the table. The leftmost cell in a row may be
grouped with the rightmost cell and the top cell in a column may be grouped with the
bottom cell.
Rolling the map
This is a group whose 1’s are already used by other groups.
Don’t care condition

•In digital systems, certain input conditions never occur during normal
operation; therefore, the corresponding output never appears.

• Since the output never appears, it is indicated by an X in the truth table.

The X is called a don 't-care condition.

•Whenever you see an X in a truth table, you can let it equal either 0 or 1,
whichever produces a simpler logic circuit.
Simplify using K-map Y=F(A,B,C,D) = ∑m (9) + d(10,11,12,13,14,15)
Give the simplest logic circuit for following logic equation where d
represents don't-care condition for following locations.
F(A, B, C, D) = ∑m(7) + d(10, 11, 12, 13, 14, 15)
Gate delays and Timing diagrams
When the input to a logic gate is changed, the output will not change
instantaneously. The gates take a finite time to react to a change in input,
so that the change in the gate output is delayed with respect to the input
change.

Timing diagrams are frequently used in the analysis of sequential circuits.

Several variables are usually plotted with the same time scale so that the
times at which these variables change with respect to each other can
easily be observed.
 If the change in output is delayed by time, ε, with
respect to the input, we say that this gate has a
Figure 8-5 shows the timing diagram for a circuit with
two gates.
We will assume that each gate has a propagation delay
of 20 ns (nanoseconds).
This timing diagram indicates what happens when gate
inputs B and C are held at constant values 1 and 0,
respectively, and input A is changed to 1 at t = 40 ns
and then changed back to 0 at t = 100 ns.
The output of gate G1 changes 20 ns after A changes,
HAZARDS IN COMBINATIONAL LOGIC
A glitch is an unwanted pulse at the output of a
combinational logic network – a momentary change in an
output that should not have changed.
A circuit with the potential for a glitch is said to have a
hazard.
In other words a hazard is something intrinsic about a circuit;
a circuit with hazard may or may not have a glitch depending
on input patterns and the electric characteristics of the circuit.
HAZARDS IN COMBINATIONAL LOGIC
When the input to a combinational circuit
changes, unwanted switching transients may
appear in the output.
These transients occur when different paths
from input to output have different
propagation delays.
If, in response to any single input change and for
some combination of propagation delays, a circuit
output may momentarily go to 0 when it should
remain a constant 1, we say that the circuit has a
static 1-hazard.
Similarly, if the output may momentarily go to 1 when
it should remain a 0, we say that the circuit has a
static 0-hazard.
If, when the output is supposed to change from 0 to 1
(or 1 to 0), the output may change three or more
times, we say that the circuit has a dynamic hazard.
The following Figure shows possible outputs from a circuit with
hazards:
Note that hazards are properties of the circuit and are
independent of the delays existing in the circuit. The
following Figure illustrates a circuit with a static 1-
hazard.
 Static-1 Hazard
● This type of hazard occurs when Y =A+
A' type of situation appears for a logic
circuit for certain combination of other
inputs and A makes a transition 1 ~ 0.
● An A + A' condition should always
generate 1 at the output, i.e. static-I. But
the NOT gate output takes finite time to
become 1 following 1 0 transition of A.
● Thus for the OR gate there are two zeros
appearing at its input for that small
duration, resulting a 0 at its output.
● For combinational circuits it may go
unnoticed but in sequential circuit, more
particularly in asynchronous sequential
circuit it may cause major malfunctioning.
To discuss how we cover static- I hazard let's look at one
example. Refer to Karnaugh map shown in Fig. 3.35a, which is
minimally represented by Y = BC' + AC. The corresponding
circuit is shown in Fig. 3.35b. Consider, for this circuit input B = 1
and A = 1 and then C makes transition 1 0. The output shows
glitch as discussed above.
We can detect hazards in a two-level AND-OR circuit,
using the following procedure:
1. Write down the sum-of-products expression for the
circuit.
2. Plot each term on the map and loop it.
3. If any two adjacent 1’s are not covered by the
same loop, a 1-hazard exists for the transition
between the two 1’s. For an n-variable map, this
transition occurs when one variable changes and the
Consider another grouping for the same map in Fig. 3.35c.
This includes one additional term AB and now output Y
=BC’+ AC+ AB.
This circuit though require more hardware than minimal
representation, is hazard free. The additional term AB ensures Y
= 1 for A = I, B = I through the third input of final OR gate and a
1 0 transition at C does not affect output.
Note that, there is no other hazard possibility and inclusion of
hazard cover does not alter the truth table in anyway.
Again, a NAND gate with A and A' connected at its input for
certain input combination will give static-I hazard when A makes
a transition
0 1 and requires hazard cover.
Static-0 Hazard
This type of hazard occurs when Y = A.A' kind of
situation occurs in a logic circuit for certain
combination of other inputs and A makes a transition
0 1.
An A.A' condition should always generate 0 at the
output, i.e. static-0. But the NOT gate output (Fig.
3.36a) takes finite time to become 0 following a 0
1 transition of A.
Thus for final AND gate there are two ones appearing
at its input for a small duration resulting a 1 at its
output (Fig. 3.36b). This Y= 1 occurs for a very small
duration (few nanosecond) but may cause
malfunctioning of sequential circuit.
Figure 3.37a shows the minimal cover in POS form
that gives Y = (B + C)(A + C') and corresponding
circuit in Fig. 3.37b. But if B = 0, A= 0 and C makes a
transition 0 1 there will be static-0 hazard occurring
at output.
To prevent this we add one additional group, i.e.
one more sum term (A+ B) as shown in Fig. 3.37c
and the corresponding circuit is shown in Fig.
3.37d.
The additional term (A + B) ensures Y = 0 for A =
0, B = 0 through the third input of final AND gate
and a 0 1 transition at C does not affect output.
Again note that for this circuit there is no other
hazard possibility and inclusion of hazard cover
does not alter the truth table in anyway.
Dynamic Hazard
Dynamic hazard occurs when circuit output
makes multiple transitions before it settles to
a final value while the logic equation asks for
only one transition.
An output transition designed as may
give
and may give when
such hazard occurs
The output of logic equation in dynamic hazard
degenerates into
Y = A + A'A or Y = (A + A')A kind of relations for certain
combinations of the other input variables.
As shown by these equations, these occur in multilevel
circuits having implicit static-I and/or static-0 hazards.
Providing covers to each one of them dynamic hazard can
be prevented.
INTRODUCTION TO HDL
HDL Hardware Description Language, is textual description of a digital circuit.

The advantage of having a HDL is course, is to be able to

(i) describe a large complex design requiring hundreds of logic gates in a

convenient manner, in a smaller space,

(ii) use software test-bench to detect functional error, if any, and correct it (called
simulation) and finally,

(iii) get hardware implementation details (called synthesis).

There are two widely used HDLs-
1. Verilog
2. VHDL (Very high speed integrated circuit Hardware Description
Language).
Verilog HDl
Verilog as a hardware description language has a small history.
Introduced in 1980, primarily as a simulation and verification tool by
Gateway Design Automation, it was later acquired by Cadence Data
Systems.
Put to public domain in 1990, it gained popularity and is now controlled by
a group of companies and universities, called Open Verilog International.
The reader with an exposure to any programming language like C will find
it relatively easier to learn Verilog or any HDL.
Describing Input/Output In any digital circuit, we find there are a set of
inputs and a set of outputs.
Often termed as ports, the relationship between these input and outputs
are explained within the digital circuit.
To design any circuit that has say, three inputs a, b, c and two outputs say,
x, y as shown in Fig. 2.37 the corresponding Verilog code can be written as
shown next.
Here module and endmodule written in bold are keywords for Verilog.
A module describes a design entity with a name or identifier selected by user
(here, testckt) followed by input output port list.
This entity if used by another then arguments (i.e. ports) are to be passed in the
same order as it appears here.
The symbol '//' is used to put comments and improve readability for a human but
not used by the machine, i.e. compiler.
The module body describes the logic within the black box which acts on the
inputs a, b, c and generates output x,y.
Observe, where semicolon';' is used and where not to end a statement, e.g.
endmodule in above code does not end with semicolon.
Writing Module Body
There are three different models of writing module body in Verilog HDL.
Each one has its own advantage and suited for certain kind of design.
We start with structural model by example of two-input OR gate
described in Fig. 2.4a.
HDl IMPLEMENTATION MODELS
There are 3 types of implementation models
Gate level modeling
Dataflow modeling
Behavioral modeling
Gate level modeling

Structural gate level modeling easily maps a digital circuit and

replicates graphical symbolic representation.
Verilog supports predefined gate level primitives such as and, or,
not, nand, nor, xor, xnor etc.
Gate level modeling, though very convenient to get started with
an HDL, consumes more space in describing a circuit and is
unsuitable for large, complex design.
Data flow modeling
Verilog provides a keyword assign and a set of operators to describe
a circuit through its behavior or function.
Here, we do not explicitly need to define any gate structure using
and, or etc. and it is not necessary to use intermediate variables
through wire showing gate level interconnections.
Verilog compiler handles this while compiling such a model.
All assign statements are concurrent, i.e. order in which they appear
do not matter and also continuous, i.e. any change in a variable in
the right hand side will immediately effect left hand side output.
Behavioral Modeling

In a behavioral model, statements are executed sequentially

following algorithmic description. It is ideally suited to describe a
sequential logic circuit. It always uses always keyword followed
by a sensitivity list.
The procedural statements following always is executed only if
any variable within sensitivity list changes its value.
Procedure assignment or output variables within always
must be of register type, defined by reg which unlike wire is
not continuously updated but only after a new value is
assigned to it.
Note that, wire variables can only be read and not assigned
to in any procedural block, also it cannot store any value and
must be continuously driven by output or assign statement.
Here, the conditional expression after if, if true
executes one set of instructions else executes a
different set following else or none at all.