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ESLint
ESLint #1383: Scheduled
July 1, 2025 10:41 1m 12s main
July 1, 2025 10:41 1m 12s
added verilog module for LSB
ESLint #1382: Pull request #621 opened by 092vk
June 29, 2025 19:28 46s 092vk:LSB
June 29, 2025 19:28 46s
added verilog module for LSB
CodeQL #1386: Pull request #621 opened by 092vk
June 29, 2025 19:28 1m 28s 092vk:LSB
June 29, 2025 19:28 1m 28s
Feat: Authentication to Tauri and Web simulator
CodeQL #1385: Pull request #554 synchronize by ThatDeparted2061
June 29, 2025 15:54 1m 30s ThatDeparted2061:auth
June 29, 2025 15:54 1m 30s
CodeQL
CodeQL #1384: Scheduled
June 29, 2025 05:34 1m 39s main
June 29, 2025 05:34 1m 39s
Added pre condition in the verilog module
ESLint #1380: Pull request #620 opened by 092vk
June 29, 2025 04:35 48s 092vk:TffFix
June 29, 2025 04:35 48s
Added pre condition in the verilog module
CodeQL #1383: Pull request #620 opened by 092vk
June 29, 2025 04:35 1m 32s 092vk:TffFix
June 29, 2025 04:35 1m 32s
Made the verilog module consistent with the Circuit simulation logic
CodeQL #1382: Pull request #619 opened by 092vk
June 29, 2025 03:14 1m 36s 092vk:DffFix
June 29, 2025 03:14 1m 36s
added verilog module for testbench element
CodeQL #1381: Pull request #611 synchronize by 092vk
June 28, 2025 14:07 1m 30s 092vk:testbenchElement
June 28, 2025 14:07 1m 30s
added verilog module for testbench element
ESLint #1378: Pull request #611 synchronize by 092vk
June 28, 2025 14:07 45s 092vk:testbenchElement
June 28, 2025 14:07 45s
Added verilog module for Force Gate
CodeQL #1380: Pull request #609 synchronize by 092vk
June 28, 2025 14:03 1m 36s 092vk:forceGate
June 28, 2025 14:03 1m 36s
Added verilog module for Force Gate
ESLint #1377: Pull request #609 synchronize by 092vk
June 28, 2025 14:03 44s 092vk:forceGate
June 28, 2025 14:03 44s
Added the Verilog Module for D-latch
CodeQL #1379: Pull request #594 synchronize by 092vk
June 28, 2025 13:45 1m 34s 092vk:dlatch
June 28, 2025 13:45 1m 34s
Added the Verilog Module for D-latch
ESLint #1376: Pull request #594 synchronize by 092vk
June 28, 2025 13:45 46s 092vk:dlatch
June 28, 2025 13:45 46s
Added Verilog Module to ALU
CodeQL #1378: Pull request #593 synchronize by 092vk
June 28, 2025 12:04 1m 38s 092vk:alu
June 28, 2025 12:04 1m 38s
Added Verilog Module to ALU
ESLint #1375: Pull request #593 synchronize by 092vk
June 28, 2025 12:04 48s 092vk:alu
June 28, 2025 12:04 48s
Added Verilog Module for SR flip flop
CodeQL #1377: Pull request #592 synchronize by 092vk
June 28, 2025 11:59 1m 35s 092vk:SRff
June 28, 2025 11:59 1m 35s
Added Verilog Module for SR flip flop
ESLint #1374: Pull request #592 synchronize by 092vk
June 28, 2025 11:59 46s 092vk:SRff
June 28, 2025 11:59 46s
Added Verilog module for JK flip flop
ESLint #1373: Pull request #591 synchronize by 092vk
June 28, 2025 11:57 2m 21s 092vk:JKff
June 28, 2025 11:57 2m 21s
Added Verilog module for JK flip flop
CodeQL #1376: Pull request #591 synchronize by 092vk
June 28, 2025 11:57 2m 23s 092vk:JKff
June 28, 2025 11:57 2m 23s
Added Verilog module for JK flip flop
ESLint #1372: Pull request #591 synchronize by 092vk
June 28, 2025 11:56 2m 49s 092vk:JKff
June 28, 2025 11:56 2m 49s
Added Verilog module for JK flip flop
CodeQL #1375: Pull request #591 synchronize by 092vk
June 28, 2025 11:56 2m 57s 092vk:JKff
June 28, 2025 11:56 2m 57s