Skip to content

introduce verilog_sva_property_typet #1081

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Draft
wants to merge 2 commits into
base: main
Choose a base branch
from
Draft

Conversation

kroening
Copy link
Member

@kroening kroening commented Apr 23, 2025

This introduces a type for Verilog SVA properties to distinguish properties from state predicates and sequences.

@kroening kroening force-pushed the verilog_sva_property_type branch from 9e75065 to d6241f6 Compare April 23, 2025 16:40
@kroening kroening force-pushed the verilog_sva_property_type branch 4 times, most recently from e0570e9 to 9b2f517 Compare May 13, 2025 19:58
@kroening kroening force-pushed the verilog_sva_property_type branch from 9b2f517 to 0905cf1 Compare June 3, 2025 19:53
This introduces a type for Verilog SVA properties to distinguish properties
from state predicates and sequences.
@kroening kroening force-pushed the verilog_sva_property_type branch from 0905cf1 to 7b91923 Compare June 5, 2025 16:47
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant