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riscv: use reg-names in machine timer driver and DTS #89847

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Merged
merged 3 commits into from
May 27, 2025

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xingrz
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@xingrz xingrz commented May 12, 2025

Since #84175, addresses of the MTIME and MTIMECMP registers are defined in DTS and retrieved using the DT_INST_REG_ADDR_BY_IDX macro.

This PR refines that approach by switching to DT_INST_REG_ADDR_BY_NAME, using the reg-names property to explicitly identify the MTIME and MTIMECMP registers. This improves readability and avoids reliance on index ordering, especially in cases where one of the registers may be absent or implemented differently.

This PR includes:

  1. An update to the riscv,machine-timer driver to use reg-names instead of register index.
  2. DTS updates to add reg-names = "mtime", "mtimecmp" to all relevant machine timer nodes.

This enhancement enables better support for platforms with nonstandard timer register layouts and serves as a prerequisite for #69594.

xingrz added 2 commits May 12, 2025 23:24
This commit updates the riscv_machine_timer driver to resolve MTIME and
MTIMECMP register addresses by their `reg-names` instead of relying on
index order.

This improves clarity and robustness in DTS bindings, and is a prerequisite
for handling cases where not both MTIME and MTIMECMP registers are present
or accessible.

Signed-off-by: Chen Xingyu <[email protected]>
This commit updates all relevant device tree source files using the
riscv,machine-timer binding to explicitly define `reg-names` for the MTIME
and MTIMECMP registers.

This change ensures compatibility with the updated riscv_machine_timer
driver, which now relies on `reg-names` to resolve register addresses
instead of using fixed index positions.

Signed-off-by: Chen Xingyu <[email protected]>
nandojve
nandojve previously approved these changes May 12, 2025
VynDragon
VynDragon previously approved these changes May 12, 2025
jimmyzhe
jimmyzhe previously approved these changes May 13, 2025
soburi
soburi previously approved these changes May 13, 2025
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It might be a good idea to mention this change in the migration guide. For users with an out of tree board and soc.

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xingrz commented May 13, 2025

It might be a good idea to mention this change in the migration guide. For users with an out of tree board and soc.

@maass-hamburg Good idea!

@VynDragon I noticed #84175 wasn’t mentioned in the 4.1 migration guide. Since this change builds on that — including the switch from compatible-based offsets to riscv,machine-timer with two reg entries, and now the move to reg-names — should we add a note covering both parts of the migration?

Clarify the changes introduced in machine timer bindings:

* Several legacy compatibles (e.g. andestech,machine-timer,
  neorv32-machine-timer, etc.) have been unified under riscv,machine-timer.
* MTIME and MTIMECMP addresses must now be specified explicitly using the
  reg and reg-names properties.
* The reg-names property is now required and must match the reg entries
  one-to-one.

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz xingrz dismissed stale reviews from soburi, jimmyzhe, VynDragon, and nandojve via 53d055f May 14, 2025 02:19
@github-actions github-actions bot added the Release Notes To be mentioned in the release notes label May 14, 2025
@xingrz xingrz requested review from soburi, VynDragon, jimmyzhe, nandojve and maass-hamburg and removed request for jimmyzhe May 14, 2025 02:26
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Summoned for a review. Presumably I'm the assignee because of the timer driver changes; dts isn't really my thing. But this all looks very reasonable.

@kartben kartben merged commit 2752814 into zephyrproject-rtos:main May 27, 2025
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@xingrz xingrz deleted the rvtimer-dts-reg-names/pr branch May 27, 2025 17:54
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area: RISCV RISCV Architecture (32-bit & 64-bit) area: Timer Timer platform: Andes Technology platform: GD32 GigaDevice Release Notes To be mentioned in the release notes
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9 participants