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riscv: use reg-names in machine timer driver and DTS #89847
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riscv: use reg-names in machine timer driver and DTS #89847
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This commit updates the riscv_machine_timer driver to resolve MTIME and MTIMECMP register addresses by their `reg-names` instead of relying on index order. This improves clarity and robustness in DTS bindings, and is a prerequisite for handling cases where not both MTIME and MTIMECMP registers are present or accessible. Signed-off-by: Chen Xingyu <[email protected]>
This commit updates all relevant device tree source files using the riscv,machine-timer binding to explicitly define `reg-names` for the MTIME and MTIMECMP registers. This change ensures compatibility with the updated riscv_machine_timer driver, which now relies on `reg-names` to resolve register addresses instead of using fixed index positions. Signed-off-by: Chen Xingyu <[email protected]>
It might be a good idea to mention this change in the migration guide. For users with an out of tree board and soc. |
@maass-hamburg Good idea! @VynDragon I noticed #84175 wasn’t mentioned in the 4.1 migration guide. Since this change builds on that — including the switch from |
Clarify the changes introduced in machine timer bindings: * Several legacy compatibles (e.g. andestech,machine-timer, neorv32-machine-timer, etc.) have been unified under riscv,machine-timer. * MTIME and MTIMECMP addresses must now be specified explicitly using the reg and reg-names properties. * The reg-names property is now required and must match the reg entries one-to-one. Signed-off-by: Chen Xingyu <[email protected]>
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Summoned for a review. Presumably I'm the assignee because of the timer driver changes; dts isn't really my thing. But this all looks very reasonable.
Since #84175, addresses of the MTIME and MTIMECMP registers are defined in DTS and retrieved using the
DT_INST_REG_ADDR_BY_IDX
macro.This PR refines that approach by switching to
DT_INST_REG_ADDR_BY_NAME
, using thereg-names
property to explicitly identify the MTIME and MTIMECMP registers. This improves readability and avoids reliance on index ordering, especially in cases where one of the registers may be absent or implemented differently.This PR includes:
riscv,machine-timer
driver to usereg-names
instead of register index.reg-names = "mtime", "mtimecmp"
to all relevant machine timer nodes.This enhancement enables better support for platforms with nonstandard timer register layouts and serves as a prerequisite for #69594.